IP Library Granted Patent US 7,644,194
Granted Patent B2
US 7,644,194 · App. 10/887,515 · Granted Jan 5, 2010

Method and system for addressing a plurality of Ethernet controllers integrated into a single chip which utilizes a single bus interface

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Quick Facts
Patent No.
US 7,644,194
App. No.
10/887,515
Granted
Jan 5, 2010
Kind
B2
Abstract

Certain embodiments of the invention may include receiving at least one message via a single bus interface to which each integrated Ethernet controller may be coupled. A bus identifier, bus device identifier and bus function identifier corresponding to the received message and which identifies a particular one of the integrated Ethernet controllers may be determined. The received message may be transferred to the particular integrated Ethernet controller based on the determined bus identifier, bus device identifier and bus function identifier, which were previously generated. The method may further include associating a bus function with the particular integrated Ethernet controller and mapping the associated bus function identifier to the bus function. A bus function process may be associated with the particular integrated Ethernet controller. The bus identifier may be associated with the single bus interface and the device identifier may be associated with the plurality of integrated Ethernet controllers.

Claims (50)

1. A method for addressing a plurality of integrated controllers, the method comprising:

receiving at least one message via a single bus interface to which each of a plurality of integrated Ethernet controllers are coupled;

determining a bus identifier, a bus device identifier and a bus function identifier of said at least one received message identifying a particular one of said integrated Ethernet controllers; and

transferring said at least one received message to said particular one of said integrated Ethernet controllers based on said determined bus identifier, said bus device identifier and said bus function identifier.

2. The method according to claim 1 , comprising associating a bus function with said particular one of said integrated Ethernet controllers.

3. The method according to claim 2 , comprising mapping said bus function identifier to said bus function.

4. The method according to claim 3 , comprising associating a bus function process with said particular one of said integrated Ethernet controllers.

5. The method according to claim 1 , comprising associating said bus identifier with said single bus interface.

6. The method according to claim 1 , comprising associating said device identifier with the plurality of said integrated Ethernet controllers.

7. The method according to claim 1 , comprising generating said at least one message comprising said bus identifier, said bus device identifier and said bus function identifier.

8. The method according to claim 1 , comprising transferring said at least one received message to said particular one of said integrated Ethernet controllers from at least one of a host processor and an on-chip processor based on said determined bus identifier, said bus device identifier and said bus function identifier.

9. The method according to claim 1 , comprising transferring said at least one received message from said particular one of said integrated Ethernet controllers to at least one of a host processor and an on-chip processor based on said determined bus identifier, said bus device identifier and said bus function identifier.

10. The method according to claim 1 , comprising processing said at least one received message by at least one of a host processor and an on-chip processor.

11. The method according to claim 1 , comprising at least one Fibre channel controller integrated with said integrated Ethernet controllers.

12. The method according to claim 1 , wherein said single bus interface is one of a PCI bus interface and a variant of said PCI bus interface.

13. A machine-readable storage having stored thereon, a computer program having at least one code section for addressing a plurality of integrated controllers, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

receiving at least one message via a single bus interface to which each of a plurality of integrated Ethernet controllers are coupled;

determining a bus identifier, a bus device identifier and a bus function identifier of said at least one received message identifying a particular one of said integrated Ethernet controllers; and

transferring said at least one received message to said particular one of said integrated Ethernet controllers based on said determined bus identifier, said bus device identifier and said bus function identifier.

14. The machine-readable storage according to claim 13 , comprising code for associating a bus function with said particular one of said integrated Ethernet controllers.

15. The machine-readable storage according to claim 14 , comprising code for mapping said bus function identifier to said bus function.

16. The machine-readable storage according to claim 15 , comprising code for associating a bus function process with said particular one of said integrated Ethernet controllers.

17. The machine-readable storage according to claim 13 , comprising code for associating said bus identifier with said single bus interface.

18. The machine-readable storage according to claim 13 , comprising code for associating said device identifier with the plurality of said integrated Ethernet controllers.

19. The machine-readable storage according to claim 13 , comprising code for generating said at least one message comprising said bus identifier, said bus device identifier and said bus function identifier.

20. The machine-readable storage according to claim 13 , comprising code for transferring said at least one received message to said particular one of said integrated Ethernet controllers from at least one of a host processor and an on-chip processor based on said determined bus identifier, said bus device identifier and said bus function identifier.

21. The machine-readable storage according to claim 13 , comprising code for transferring said at least one received message from said particular one of said integrated Ethernet controllers to at least one of a host processor and an on-chip processor based on said determined bus identifier, said bus device identifier and said bus function identifier.

22. The machine-readable storage according to claim 13 , comprising code for processing said at least one received message by at least one of a host processor and an on-chip processor.

23. The machine-readable storage according to claim 13 , wherein at least one Fibre channel controller is integrated with said integrated Ethernet controller.

24. The machine-readable storage according to claim 13 , wherein said single bus interface is one of a PCI bus interface and a variant of said PCI bus interface.

25. A system for addressing a plurality of integrated controllers, the system comprising:

an arbiter that receives at least one message via a single bus interface to which each of a plurality of integrated Ethernet controllers are coupled;

said arbiter determines a bus identifier, a bus device identifier and a bus function identifier of said at least one received message identifying a particular one of said integrated Ethernet controllers; and

said arbiter transfers said at least one received message to said particular one of said integrated Ethernet controllers based on said determined bus identifier, said bus device identifier and said bus function identifier.

26. The system according to claim 25 , wherein said arbiter associates a bus function with said particular one of said integrated Ethernet controllers.

27. The system according to claim 26 , wherein said arbiter maps said bus function identifier to said bus function.

28. The system according to claim 27 , wherein said arbiter associates a bus function process with said particular one of said integrated Ethernet controllers.

29. The system according to claim 25 , wherein said arbiter associates said bus identifier with said single bus interface.

30. The system according to claim 25 , wherein said arbiter associates said device identifier with the plurality of said integrated Ethernet controllers.

31. The system according to claim 25 , wherein said arbiter generates said at least one message comprising said bus identifier, said bus device identifier and said bus function identifier.

32. The system according to claim 25 , wherein said arbiter transfers said at least one received message to said particular one of said integrated Ethernet controllers from at least one of a host processor and an on-chip processor based on said determined bus identifier, said bus device identifier and said bus function identifier.

33. The system according to claim 25 , wherein said arbiter transfers said at least one received message from said particular one of said integrated Ethernet controllers to at least one of a host processor and an on-chip processor based on said determined bus identifier, said bus device identifier and said bus function identifier.

34. The system according to claim 25 , wherein said arbiter processes said at least one received message by at least one of a host processor and an on-chip processor.

35. The system according to claim 25 , comprising at least one Fibre channel controller integrated with said integrated Ethernet controllers.

36. The system according to claim 25 , wherein said single bus interface is one of a PCI bus interface and a variant of said PCI bus interface.

37. The system according to claim 25 , comprising at least one bus function associated with said particular one of said integrated Ethernet controllers.

38. The system according to claim 37 , comprising at least one bus process associated with said at least one bus function and said particular one of said integrated Ethernet controllers.

39. The system according to claim 38 , wherein said arbiter routes said at least one message to said particular one of said integrated Ethernet controllers, said at least one bus function and said at least one bus process via said single bus interface.

40. The system according to claim 25 , wherein said bus identifier is similar for said each of said integrated Ethernet controllers coupled via said single bus interface.

41. The system according to claim 25 , wherein said bus device identifier is similar for said each of said integrated Ethernet controllers coupled via said single bus interface.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2004
From: LINDSAY, STEVEN B.; ALVSTAD, GARY
To: BROADCOM CORPORATION
Reel/Frame 015096/0947 →