Circuit arrangement for operating at least one high-pressure discharge lamp
View Patent ↗A circuit arrangement for operating at least one high-pressure discharge lamp ( 16 ), has four switches (Q 1 to Q 4 ) in a full-bridge arrangement ( 14 ), a first and a second switch (Q 1 , Q 2 ) forming the first half-bridge arm, and a third and a fourth switch (Q 3 , Q 4 ) forming the second half-bridge arm, at least two terminals for coupling the high-pressure discharge lamp ( 16 ) between the midpoint of the first and the second half-bridge arms, at least two terminals for supplying the circuit arrangement ( 10 ) with a dc voltage signal and a drive circuit ( 20 ) for driving the four switches (Q 1 to Q 4 ). The drive circuit ( 20 ) is designed to provide drive signals, (z 1 (t), z 2 (t), z 1 (t), z 2 (t)) for the four switches (Q 1 to Q 4 ), whose clock pulse (f t ) is swept between a first and a second frequency, and whose pulse width and/or phase is modulated with a prescribable third frequency (f a ).
1. A circuit arrangement for operating at least one high-pressure discharge lamp comprising:
four switches in a full-bridge arrangement, a first and a second switch forming the first half-bridge arm, and a third and a fourth switch forming the second half-bridge arm,
at least two terminals for coupling the high-pressure discharge lamp between the midpoint of the first and the second half-bridge arms,
at least two terminals for supplying the circuit arrangement with a dc voltage signal and
a drive circuit for driving the four switches,
wherein the drive circuit is designed to provide drive signals, for the four switches, whose clock pulse is swept between a first and a second frequency, and whose pulse width and/or phase is modulated with a prescribable third frequency, and
wherein the drive circuit comprises a PWM module whose clock input is coupled to a first source for the clock pulse swept between the first and the second frequencies, and whose modulation input is coupled to a second source for the signal at the third frequency.
2. The circuit arrangement as claimed in claim 1 ,
wherein the clock frequency is below 150 kHz.
3. The circuit arrangement as claimed in claim 1 ,
wherein the third frequency is below 50 kHz.
4. The circuit arrangement as claimed in claim 1 ,
wherein the sweep frequency is between 50 Hz and 500 Hz.
5. The circuit arrangement as claimed in claim 1 ,
wherein the drive circuit is designed to drive the switches of the full-bridge arrangement with dual-alternating complementary signals.
6. The circuit arrangement as claimed in claim 1 ,
wherein the pulse width is modulated asymmetrically.
7. The circuit arrangement as claimed in claim 1 ,
wherein the pulse width is modulated symmetrically.
8. The circuit arrangement as claimed in claim 1 ,
wherein the modulation input of the PWM module is furthermore coupled to a source for an offset signal.
9. The circuit arrangement as claimed in claim 1 ,
wherein the drive circuit comprises a phase shift module whose clock input is coupled to a source for the clock pulse swept between the first and the second frequencies, and whose modulation input is coupled to a source for the signal at the third frequency.
10. The circuit arrangement as claimed in claim 2 ,
wherein the clock frequency is between 40 and 60 kHz.
11. The circuit arrangement as claimed in claim 2 ,
wherein the clock frequency is between 80 and 120 kHz.
12. The circuit arrangement as claimed in claim 3 ,
wherein the third frequency is between 20 and 35 kHz.
13. The circuit arrangement as claimed in claim 4 ,
wherein the sweep frequency is between 80 Hz and 200 Hz.