Integrated semiconductor power device for multiple battery systems

1. An integrated semiconductor device comprising:

a semiconductor die having a charging path and a discharging path; and

three independently operable semiconductor devices formed in said die at least one of which is in said charging path and at least another one of which is in said discharging path, each said device including

a first power electrode,

a control electrode, and

a second power electrode;

wherein said first power electrode and said control electrode of each die is disposed on a first major surface of said semiconductor die, and said second power electrode is disposed on a second opposing major surface of said semiconductor die and is common to all said devices, and wherein said at least one device in said charging path is configured to have a different on resistance than that of said at least another device.

2. A semiconductor device according to claim 1 , wherein said first power electrode is a source electrode, said control electrode is a gate electrode, and said second power electrode is a drain electrode.

3. A semiconductor device according to claim 1 , wherein said first power electrode is adapted for flip-chip mounting.

4. A semiconductor device according to claim 1 , wherein said first power electrode includes solder bumps for flip-chip mounting.

5. A semiconductor device according to claim 1 , wherein there are three power MOSFETs formed in said semiconductor die.

6. An integrated semiconductor device comprising:

a silicon die having a charging path and a discharging path; and

a plurality of independently operable power MOSFETs formed in said silicon die at least one of said MOSFETs being in said charging path and at least another one of said MOSFETs being in said discharging path, each said power MOSFET including

a source electrode,

a gate electrode, and

a drain electrode;

wherein said source electrode and said gate electrode of each die is disposed on a first major surface of said silicon die, and said drain electrode is disposed on a second opposing major surface of said silicon die and common to all said MOSFETs wherein said MOSFET in said charging path has an on resistance that is different from that of said MOSFET in said discharging path.

7. A semiconductor device according to claim 6 , wherein said source electrode is adapted for flip-chip mounting.

8. A semiconductor device according to claim 6 , wherein said source electrode includes solder bumps for flip-chip mounting.

9. A semiconductor device according to claim 6 , wherein there are three power MOSFETs formed in said silicon die.