Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit
View Patent ↗In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.
1. A semiconductor integrated circuit device, comprising:
a main circuit comprising a first MOS transistor of a first conductivity type, the source and drain region of the first MOS transistor being formed on a first semiconductor region of a second conductivity type;
a substrate bias generator to supply a substrate bias voltage to the first semiconductor region, the substrate bias voltage ranging from a back bias voltage to a forward bias voltage;
a current limiting circuit coupled between the first semiconductor region and the substrate bias generator, to limit the current flowing through the first semiconductor region; and
a substrate current detection circuit to detect the current flowing through the first semiconductor region,
wherein the substrate current detection circuit controls the current limiting circuit according to the current flowing through the first semiconductor region.
2. A semiconductor integrated circuit device according to claim 1 ,
wherein the substrate current detection circuit comprises:
a leak current measuring circuit to output a first potential according to the current flowing through the first semiconductor region,
wherein the substrate current detection circuit controls the current limiting circuit according to the value of the first potential.
3. A semiconductor integrated circuit device according to claim 2 ,
wherein the substrate current detection circuit further comprises:
a first comparator to compare the first potential with a first reference potential, and to output a first signal,
wherein the first comparator outputs the first signal until the first potential is higher than the first reference potential.
4. A semiconductor integrated circuit device according to claim 2 ,
wherein the substrate current detection circuit further comprises:
a second comparator to compare the first potential with a second reference potential, and to output a second signal,
wherein the second comparator outputs the second signal until the first potential is lower than the second reference potential.
5. A semiconductor integrated circuit device according to claim 2 ,
wherein the substrate current detection circuit further comprises:
a first comparator to compare the first potential with a first reference potential, and to output a first signal; and
a second comparator to compare the first potential with a second reference potential, and to output a second signal,
wherein the first comparator outputs the first signal until the first potential is higher than the first reference potential, and the second comparator outputs the second signal until the first potential is lower than the second reference potential.
6. A semiconductor integrated circuit device according to claim 2 ,
wherein the leak current measuring circuit comprises:
a first resistor coupled to a first potential point and to the first semiconductor region, the potential of the first potential point being higher than the first potential;
a second resistor coupled to the first semiconductor region and to a second potential point, the potential of the third potential being lower than the first potential; and
a node coupled to the first resistor and to the first semiconductor region, to output the first potential.
7. A semiconductor integrated circuit device according to claim 6 ,
wherein the first resistor is coupled to a diffusion layer of a first conductivity type, the diffusion layer is coupled to the first semiconductor region, and the first semiconductor region is coupled to a substrate isolation layer of a first conductivity type,
wherein a leakage current flows through the diffusion layer, the first semiconductor region, and the substrate isolation layer, and
wherein the first conductivity type is N-type, and the second conductivity type is P-type.
8. A semiconductor integrated circuit device according to claim 6 ,
wherein the first resistor is coupled to a diffusion layer of a first conductivity type, the diffusion layer is coupled to the first semiconductor region, the first semiconductor region is coupled to a substrate isolation layer of a second conductivity type, and the substrate isolation layer is coupled to a substrate of a first conductivity type,
wherein a leakage current flows through the diffusion layer, the first semiconductor region, the substrate isolation layer, and the substrate, and
wherein the first conductivity type is P-type, and the second conductivity is N-type.
9. A method of supplying a substrate bias voltage, comprising:
providing a semiconductor integrated circuit device including a main circuit comprising a first MOS transistor of a first conductivity type, the source and drain of the first MOS transistor being formed on a first semiconductor region of a second conductivity type, and a substrate bias generator supplying the substrate bias voltage, the substrate bias voltage ranging from a back bias voltage to a forward bias voltage;
detecting the current flowing through the first semiconductor region; and
limiting the current flowing through the first semiconductor region,
wherein limiting the current flowing through the first semiconductor region is controlled by detecting the current flowing through the semiconductor region.
10. A method of supplying a substrate bias voltage according to claim 9 , further comprising:
outputting a first potential according to the current flowing through the first semiconductor region; and
adjusting the current flowing through the first semiconductor region according to the first potential.
11. A method of supplying a substrate bias voltage according to claim 10 , further comprising:
comparing the first potential with a first reference potential; and
outputting a first signal until the first potential is higher than the first reference potential.
12. A method of supplying a substrate bias voltage according to claim 10 , further comprising:
comparing the first potential with a second reference potential; and
outputting a second signal until the first potential is lower than the second reference potential.
13. A method of supplying a substrate bias voltage according to claim 10 , further comprising:
comparing the first potential with a first reference potential;
comparing the first potential with a second reference potential;
outputting a first signal until the first potential is higher than the first reference potential; and
outputting a second signal until the first potential is lower than the second reference potential.
14. A method of supplying a substrate bias voltage according to claim 10 , further comprising:
outputting the first potential from a node,
wherein the node is coupled to a first resistor and the first semiconductor region, the first resistor is coupled to a first potential point, the first semiconductor region is coupled to a second resistor, and the second resistor is coupled to a second potential point.
15. A method of supplying a substrate bias voltage according to claim 14 , wherein the first resistor is coupled to a diffusion layer of a first conductivity type, the diffusion layer is coupled to the first semiconductor region, and the first semiconductor region is coupled to a substrate isolation layer of a first conductivity type,
wherein a leakage current flows through the diffusion layer, the first semiconductor region, and the substrate isolation layer, and
wherein the first conductivity type is N-type, and the second conductivity-type is P-type.
16. A method of supplying a substrate bias voltage according to claim 14 ,
wherein the first resistor is coupled to a diffusion layer of a first conductivity type, the diffusion layer is coupled to the first semiconductor region, the first semiconductor region is coupled to a substrate isolation layer of a second conductivity type, and the substrate isolation layer is coupled to a substrate of a first conductivity type,
wherein a leakage current flows through a the diffusion layer, the semiconductor region, the substrate isolation layer, and the substrate; and
wherein the first conductivity type is P-type, and the second conductivity type is N-type.