Symmetric charge pump
View Patent ↗A charge pump is disclosed which generates higher and more symmetric source and sink currents that prior designs and reduces the multiple frequency sidebands that occur in a voltage controlled oscillator of a phase-loop synthesizer. Other improvements are the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked designs for single chip CMOS multi-band and multi-standard radio frequency integrated circuits.
1. A charge pump having improved symmetry that limits the reference frequency feed-though of clocking signals generated from a phase frequency detector comprising:
a differential buffer responsive to the clocking signals and providing a first output and a second output;
a pull-up current source responsive to the first output and providing a pull-up current; and
a transmission switch responsive to the first and second outputs for increasing turn off speed of said pull-up current source, wherein the transmission switch includes
a complementary transmission gate coupled to the pull-up current source and a bias supply coupled between the complementary transmission gate and ground.
2. The charge pump of claim 1 further comprising:
a second differential buffer responsive to the clocking signals and providing a third output and a fourth output;
a pull-down current sink responsive to the third output and providing a pull-down current; and
a second transmission switch responsive to the third and fourth outputs for increasing turn off speed of said pull-down current sink.
3. The charge pump of claim 2 , wherein the second transmission switch includes
a second complementary transmission gate coupled to the pull-down current sink and to the bias supply.
4. The charge pump of claim 2 , wherein the second transmission switch includes
a second complementary transmission gate coupled to the pull-down current sink and a second bias supply coupled between the second complementary transmission gate and ground.
5. The charge pump of claim 2 , further including
a CMOS dummy load network to equalize the loading capacitance of the complementary transmission gate.
6. The charge pump of claim 3 , further including
a CMOS dummy load network to equalize the loading capacitance of the second complementary transmission gate.
7. The charge pump of claim 3 , further including
a first CMOS dummy load network to equalize the loading capacitance of the complementary transmission gate; and
a second CMOS dummy load network to equalize the loading capacitance of the second complementary transmission gate.
8. The charge pump of claim 4 , further including
a CMOS dummy load network to equalize the loading capacitance of the second complementary transmission gate.
9. The charge pump of claim 4 , further including
a first CMOS dummy load network to equalize the loading capacitance of the complementary transmission gate; and
a second CMOS dummy load network to equalize the loading capacitance of the second complementary transmission gate.
10. A method of charge pumping having improved symmetry that limits the reference frequency feed-though of clocking signals generated from a phase frequency detector comprising:
differentially buffering the clocking signals to provide a first output and a second output;
providing a pull-up current, with a pull-up current source, responsive to the first output; and
increasing turn off speed of said pull-up current source using a transmission switch responsive to the first and second outputs, wherein the transmission switch includes
a complementary transmission gate coupled to the pull-up current source and a bias supply coupled between the complementary transmission gate and ground.
11. The method of claim 10 further comprising:
differentially buffering the clocking signals to provide a third output and a fourth output;
providing a pull-down current, with a pull-down current sink, responsive to the third output and providing a pull-down current; and
increasing turn off speed of said pull-down current sink using a second transmission switch responsive to the third and fourth outputs.
12. The method of claim 11 , wherein the second transmission switch includes
a second complementary transmission gate coupled to the pull-down current sink and to the bias supply.
13. The method of claim 11 , wherein the second transmission switch includes
a second complementary transmission gate coupled to the pull-down current sink and a second bias supply coupled between the second complementary transmission gate and ground.
14. The method of claim 11 , further including
equalizing the loading capacitance of the complementary transmission gate with a CMOS dummy load network.
15. The method of claim 12 , further including
equalizing the loading capacitance of the second complementary transmission gate with a CMOS dummy load network.
16. The method of claim 12 , further including
equalizing the loading capacitance of the complementary transmission gate with a first CMOS dummy load network; and
equalizing the loading capacitance of the second complementary transmission gate with a second CMOS dummy load network.
17. The method of claim 13 , further including
equalizing the loading capacitance of the second complementary transmission gate with a CMOS dummy load network.
18. The method of claim 13 , further including
equalizing the loading capacitance of the complementary transmission gate with a first CMOS dummy load network; and
equalizing the loading capacitance of the second complementary transmission gate with a second CMOS dummy load network.