IP Library Granted Patent US 7,145,368
Granted Patent B2
US 7,145,368 · App. 10/890,154 · Granted Dec 5, 2006

Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method

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Quick Facts
Patent No.
US 7,145,368
App. No.
10/890,154
Granted
Dec 5, 2006
Kind
B2
Abstract

A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Claims (14)

1. A clock signal switching device comprising:

first signal synchronization generation means for generating, based on a switching signal used in selecting either a first clock signal or a second clock signal and based on the first clock signal, a first mask signal and a first synchronized switching signal each synchronous with the first clock signal;

second signal synchronization generation means for generating, based on the switching signal and the second clock signal, a second mask signal and a second synchronized switching signal each synchronous with the second clock signal;

first clock signal mask means for masking the first clock signal with the first mask signal, thereby generating a first masked clock signal;

second clock signal mask means for masking the second clock signal with the second mask signal, thereby generating a second masked clock signal;

synchronized switching signal selection means for selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal; and

masked clock signal selection means for selecting either the first masked clock signal or the second masked clock signal as a selected clock signal based on the selected switching signal.

2. The device of claim 1 , wherein the first clock signal and the second clock signal have different frequencies.

3. The device of claim 1 , wherein the first clock signal and the second clock signal are out of phase with each other.

4. A data receiving device comprising:

at least one said clock signal switching device of claim 1 as signal switching means;

first receiving means for outputting a first externally received clock signal to the signal switching means;

second receiving means for outputting a second externally received clock signal to the signal switching means; and

transmitting means for externally transmitting the selected clock signal selected by the signal switching means.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021930/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2004
From: HASHIMOTO, SHINICHI; YOSHIDA, TADAHIRO; YANAGISAWA, RYOGO
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 015581/0492 →