Semiconductor integrated circuit device and method of manufacturing the same
View Patent ↗A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 μm, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
1. A semiconductor integrated circuit device comprising:
a wire electrically connected to a surface electrode of a semiconductor chip;
a plurality of inner leads located around said semiconductor chip;
a palladium layer formed over a wire bonding portion of each of said plurality of inner leads;
an adhered portion formed by connection of said wire with one of said inner leads; and
a resin for molding said semiconductor chip, said plurality of inner leads, said wire and said adhered portion,
wherein a diameter of said wire is 30 μm or less,
wherein said adhered portion has an adhered width and an adhered length,
wherein said adhered width is 1.5 times or more said diameter of said wire, and said adhered width is 3.5 times or less said diameter of said wire, and
wherein said adhered length is 1.5 times or more said diameter of said wire, and said adhered length is 3.5 times or less said diameter of said wire.
2. A semiconductor integrated circuit device comprising:
a die pad supporting a semiconductor chip;
a wire electrically connected to a surface electrode of said semiconductor chip;
a plurality of inner leads located around said semiconductor chip;
a palladium layer formed over a wire bonding portion of each of said plurality of inner leads;
an adhered portion formed by connection of said wire with one of said inner leads; and
a resin for molding said semiconductor chip, said plurality of inner leads, said wire and said adhered portion,
wherein a diameter of said wire is 30 μm or less,
wherein said adhered portion has an adhered width and an adhered length,
wherein said adhered width is 1.5 times or more said diameter of said wire, and said adhered width is 3.5 times or less said diameter of said wire, and
wherein said adhered length is 1.5 times or more said diameter of said wire, and said adhered length is 3.5 times or less said diameter of said wire.
3. A semiconductor integrated circuit device according to claim 2 , wherein said palladium layer is formed over said die pad.
4. A semiconductor integrated circuit device comprising:
a wire electrically connected to a surface electrode of a semiconductor chip;
a plurality of inner leads located around said semiconductor chip;
a palladium layer formed over a wire bonding portion of each of said plurality of inner leads;
an adhered portion formed by connection of said wire with one of said inner leads;
a resin for molding said semiconductor chip, said plurality of inner leads, said wire and said adhered portion,
wherein a diameter of said wire is 30 μm or less,
wherein said adhered portion has an adhered width and an adhered length, and
means for preventing wire disconnection between said wire and said one of said inner leads by setting the size of the adhered portion such that said adhered width is 1.5 times or more said diameter of said wire, and said adhered width is 3.5 times or less said diameter of said wire, and said adhered length is 1.5 times or more said diameter of said wire and said adhered length is 3.5 times or less said diameter of said wire.