Method and system for dynamically configurable DCT/IDCT module in a wireless handset

1. A method for signal processing, the method comprising:

performing, by one or more processors and/or circuits integrated within a single chip, functions comprising:

determining a video codec format mode of operation and a quantization scheme from a plurality of video codec format modes of operation and a plurality of quantization schemes based on a received video signal;

configuring a processing network according to said determined video codec format mode of operation and quantization scheme and based on whether said received video signal is to be encoded or decoded; and

processing said received video signal using said configured processing network.

2. The method according to claim 1 , said functions comprising configuring said processing network into a DCT processing network configuration when said received video signal is to be encoded.

3. The method according to claim 1 , said functions comprising configuring said processing network into an IDCT processing network configuration when said received video signal is to be decoded.

4. The method according to claim 1 , said functions further comprising storing said processed received video signal into a memory.

5. The method according to claim 1 , said functions further comprising determining whether said determined video codec format mode of operation is associated with a JPEG video codec format, an MPEG video codec format, or an H.263 video codec format.

6. The method according to claim 1 , said functions further comprising programming a plurality of JPEG luminance quantization values to be utilized by said processing network.

7. The method according to claim 1 , said functions further comprising programming a plurality of JPEG chrominance quantization values to be utilized by said processing network.

8. The method according to claim 1 , said functions further comprising programming a plurality of MPEG intraframe quantization values to be utilized by said processing network.

9. The method according to claim 1 , said functions further comprising programming a plurality of MPEG interframe quantization values to be utilized by said processing network.

10. The method according to claim 1 , said functions further comprising determining an MPEG luminance DC scaling factor based on a quantization parameter.

11. The method according to claim 1 , said functions further comprising determining an MPEG chrominance DC scaling factor based on a quantization parameter.

12. A system for signal processing, the system comprising:

one or more processors and/or circuits integrated within a single chip, wherein said one or more processors and/or circuits are operable to:

determine a video codec format mode of operation and a quantization scheme from a plurality of video codec format modes of operation and a plurality of quantization schemes based on a received video signal;

configure a processing network within said single chip according to said determined video codec format mode of operation and quantization scheme and based on whether said received video signal is to be encoded or decoded; and

process said received video signal using said configured processing network.

13. The system according to claim 12 , wherein said one or more processors and/or circuits comprise a memory operable to store said processed received video signal.

14. The system according to claim 12 , wherein said one or more processors and/or circuits comprise a DCT/IDCT module that comprises a buffer, an adder/subtractor, a multiplier/accumulator, a plurality of digital dividers, and a de-quantizer.

15. The system according to claim 14 , wherein said plurality of digital dividers comprise a 12-bit divider and a 7-bit divider.

16. The system according to claim 14 , wherein said buffer is an 8-element circular FIFO.

17. The system according to claim 14 , wherein said at least one processor one or more processors and/or circuits are operable to configure said DCT/IDCT module into a DCT processing network configuration when said received video signal is to be encoded.

18. The system according to claim 14 , wherein said at least one processor one or more processors and/or circuits are operable to configure said DCT/IDCT module into an IDCT processing network configuration when said received video signal is to be decoded.

19. The system according to claim 14 , wherein said one or more processors and/or circuits are operable to modify said DCT/IDCT module to operate in said determined video format mode of operation.

20. The system according to claim 14 , wherein said one or more processors and/or circuits are operable to program a plurality of JPEG luminance quantization values to be utilized by said DCT/IDCT module.

21. The system according to claim 14 , wherein said one or more processors and/or circuits are operable to program a plurality of JPEG chrominance quantization values to be utilized by said DCT/IDCT module.

22. The system according to claim 14 , wherein said one or more processors and/or circuits are operable to program a plurality of MPEG intraframe quantization values to be utilized by said DCT/IDCT module.

23. The system according to claim 14 , wherein said one or more processors and/or circuits are operable to program a plurality of MPEG interframe quantization values to be utilized by said DCT/IDCT module.

24. The system according to claim 12 , wherein said one or more processors and/or circuits are operable to determine an MPEG luminance DC scaling factor based on a quantization parameter.

25. The system according to claim 12 , wherein said one or more processors and/or circuits are operable to determine an MPEG chrominance DC scaling factor based on a quantization parameter.

26. An encoding network configuration, the encoding network configuration comprising:

a FIFO;

an adder/subtractor coupled to said FIFO;

a multiplier accumulator coupled to said adder/subtractor;

a first bit width reduction block coupled to said multiplier/accumulator;

an M-bit divider coupled to said first bit width reduction block; and

a second bit width reduction block coupled to said M-bit divider.

27. The encoding network configuration of claim 26 , wherein said encoding network configuration receives a video signal for encoding in JPEG video format or H.263 video format.

28. The encoding network configuration of claim 26 , wherein said M-bit divider is a 12-bit divider.

29. The encoding network configuration of claim 26 , further comprising:

an N-bit divider coupled to said second bit width reduction block; and

a third bit width reduction block coupled to said N-bit width divider.

30. The encoding network configuration of claim 29 , wherein said N-bit divider is a 7-bit divider.

31. The encoding network configuration of claim 29 , wherein said encoding network configuration receives a video signal for encoding in MPEG video format.

32. An decoding network configuration, the decoding network configuration comprising:

a de-quantizer;

a first bit width reduction block coupled to said de-quantizer;

a multiplier/accumulator coupled to said first bit width reduction block;

a FIFO coupled to said multiplier/accumulator;

a second bit width reduction block coupled to said FIFO;

an adder/subtractor coupled to said second bit width reduction block; and

a third bit width reduction block coupled to said adder/subtractor.

33. The decoding network configuration of claim 32 , wherein said decoding network configuration receives a video signal in JPEG, MPEG, or H.263 video format for decoding.

34. The method according to claim 1 , wherein each of said plurality of video codec format modes of operation is associated with one or more quantization schemes from said plurality of quantization schemes.

35. The system according to claim 12 , wherein each of said plurality of video codec format modes of operation is associated with one or more quantization schemes from said plurality of quantization schemes.

36. An apparatus for signal processing, comprising:

one or more processors and/or circuits integrated within a single chip operable to determine, based on a received video signal, a video codec standard format mode of operation from a plurality of video codec standard format modes of operation supported by the one or more processors and/or circuits integrated within the single chip, each of the plurality of video codec standard format modes of operation having one or more associated quantization schemes;

wherein the one or more processors and/or circuits integrated within the single chip comprise a plurality of modules configured into a network based on the determined video codec standard format mode of operation and based on whether the received video signal is to be encoded or decoded, and

wherein the one or more processors and/or circuits integrated within the single chip are operable to process the received video using the configured network of modules.