Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication

1. A multiply execution unit that is operable to generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier, the multiply execution unit comprising:

a summing circuit for summing a plurality of partial products, the summing circuit including a plurality of rows, the summing circuit operable to generate an integer sum of the plurality of partial products and operable to generate an XOR sum of the plurality of partial products, the summing circuit including:

a plurality of compressors in the first row of the summing circuit, the plurality of compressors each having more than three inputs that receive data, a carry output, and a sum output.

2. The multiply execution unit of claim 1 , wherein the plurality of compressors include at least one 4:2 compressor.

3. The multiply execution unit of claim 2 , wherein the plurality of compressors include at least one compressor that includes a majority gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

4. The multiply execution unit of claim 3 , wherein the majority gate includes four NAND gates.

5. The multiply execution unit of claim 3 , wherein the majority gate outputs a “0” if an XOR sum is to be determined.

6. The multiply execution unit of claim 2 , wherein the plurality of compressors includes at least one compressor that includes an AND gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

7. The multiply execution unit of claim 6 wherein the AND gate outputs a “0” if an XOR sum is to be determined.

8. The multiply execution unit of claim 1 , wherein the plurality of compressors include at least one 5:3 compressor.

9. The multiply execution unit of claim 8 , wherein the plurality of compressors include at least one compressor that includes a majority gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

10. The multiply execution unit of claim 9 , wherein the majority gate includes four NAND gates.

11. The multiply execution unit of claim 9 , wherein the majority gate outputs a “0” if an XOR sum is to be determined.

12. The multiply execution unit of claim 8 , wherein the plurality of compressors includes at least one compressor that includes an AND gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

13. The multiply execution unit of claim 12 , wherein the AND gate outputs a “0” if an XOR sum is to be determined.

14. The multiply execution unit of claim 1 , wherein the more than three inputs each receive a signal from a Booth encoder.

15. The multiply execution unit of claim 1 , wherein the plurality of compressors include at least one compressor that includes a majority gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

16. The multiply execution unit of claim 15 , wherein the majority gate includes four NAND gates.

17. The multiply execution unit of claim 15 , wherein the majority gate outputs a “0” if an XOR sum is to be determined.

18. The multiply execution unit of claim 1 , wherein the summing circuit includes: a second plurality of compressors in the second row of the summing circuit, the second plurality of compressors each having more than three inputs that receive data, a carry output, and a sum output.

19. The multiply execution unit of claim 18 , wherein the second plurality of compressors include at least one 4:2 compressor.

20. The multiply execution unit of claim 18 , wherein the second plurality of compressors include at least one 5:3 compressor.

21. The multiply execution unit of claim 18 , wherein the second plurality of compressors include at least one compressor that includes a majority gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

22. The multiply execution unit of claim 21 , wherein the majority gate includes four NAND gates.

23. The multiply execution unit of claim 21 , wherein the majority gate outputs a “0” if an XOR sum is to be determined.

24. The multiply execution unit of claim 21 , wherein the first plurality of compressors and the second plurality of compressors both include at least one 4:2 compressor.

25. The multiply execution unit of claim 21 , wherein the first plurality of compressors and the second plurality of compressors both include at least one 5:3 compressor.

26. The multiply execution unit of claim 18 , wherein the second plurality of compressors includes at least one compressor that includes an AND gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

27. The multiply execution unit of claim 26 , wherein the AND gate outputs a “0” if an XOR sum is to be determined.

28. The multiply execution unit of claim 26 , wherein the first plurality of compressors and the second plurality of compressors both include at least one 4:2 compressor.

29. The multiply execution unit of claim 26 , wherein the first plurality of compressors and the second plurality of compressors both include at least one 5:3 compressor.

30. The multiply execution unit of claim 1 , wherein the plurality of compressors includes at least one compressor that includes an AND gate that receives an input that indicates whether an XOR sum or an integer sum is to be determined.

31. The multiply execution unit of claim 30 , wherein the AND gate outputs a “0” if an XOR sum is to be determined.