Assertion morphing in functional verification of integrated circuit design
View Patent ↗A method and apparatus provides a mechanism to transform or “morph” Formal verification method assertions so that an assertion defined in one Design Under Test (DUT) can be replicated, or derived, to propagate into other related DUTs. Using the method and apparatus of the present invention, individual DUTs can better leverage assertions defined independently in other DUT environments. This, in turn, provides for greater productivity and a faster, smoother verification process-using Formal and Assertion Based Verification methods.
1. A method for deriving assertions so that an assertion defined in one Design Under Test (DUT) can be replicated to propagate into other related DUTs, said method comprising:
providing a system level DUT comprised of at least one block level DUT;
preparing a list of Formal verification method assertions for each block level DUT of said system level DUT;
identifying equivalent assertions from a list of all block level DUTs comprising said system level DUT;
keeping only unique assertions, either generated originally or as a derivative, in each block level DUT environment;
keeping derived assertions shared by one or more DUTs; and,
removing all redundant assertions.
2. A method for deriving assertions so that an assertion defined in one Design Under Test (DUT) can be replicated to propagate into other related DUTs, said method comprising:
providing a system level DUT comprised of at least one block level DUT;
defining assertions in the individual block
preparing a list of all assertions in the individual block level DUT environments;
requiring design engineers to check all potentially “new” assertions against said list of all assertions in the individual block level DUT environments and adding equivalent assertions to each individual DUT environment whenever an assertion is added;
preparing a list of Formal verification method assertions for each block level DUT of said system level DUT;
identifying equivalent assertions identified from collected assertions of all block level DUTs comprising said system level DUT;
keeping only unique assertions, either generated originally or as a derivative, in each block DUT environment;
keeping derived assertions shared by one or more DUTs; and,
removing all redundant assertions.
3. The method for deriving assertions so that an assertion defined in one DUT can be replicated to propagate into other related DUTs of claim 2 , wherein;
a centralized file is created to keep track of the assertions on a given system level design, further wherein;
if one designer wishes to add or change an assertion in a given block level DUT, the designer writes the assertion in an appropriate assertion description language and makes the assertion available to any verification tool for access.
4. The method for deriving assertions so that an assertion defined in one DUT can be replicated to propagate into other related DUTs of claim 3 , wherein;
if one designer adds or changes an assertion in a given block level DUT, an electronic notification is automatically sent to all affected designers asking them to derive the assertion into their block level DUTs.
5. The method for deriving assertions so that an assertion defined in DUT can be replicated to propagate into other related DUTs of claim 4 , wherein;
said electronic notification is an e-mail.
6. A method for deriving assertions so that an assertion defined in one Design Under Test (DUT) can be replicated to propagate into other related DUTs, said method comprising:
providing a system level DUT comprised of at least one block level DUT;
defining assertions in the individual block level DUT environments;
preparing a list of all assertions in the individual block level DUT environments; and
for each assertion in said list of all assertions in the individual block level DUT environments replicating said each assertion by replacing an involved signal with a corrected signal in a different DUT to form a new assertion.
7. A method for deriving assertions so that an assertion defined in one Design Under Test (DUT) can be replicated to propagate into other related DUTs said method comprising:
providing a system level DUT comprised of at least one block level DUT;
defining assertions in individual block level DUT environments;
preparing a list of all assertions in the individual block level DUT environments;
for each assertion in said list of all assertions in the individual block level DUT environments, propagating signals to all other DUTs; and
constructing a derived assertion direct connections.