IP Library Granted Patent US 7,411,947
Granted Patent B2
US 7,411,947 · App. 10/893,912 · Granted Aug 12, 2008

Storage system, computer system and interface module

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Quick Facts
Patent No.
US 7,411,947
App. No.
10/893,912
Granted
Aug 12, 2008
Kind
B2
Abstract

An interface module comprises a serial signal transceiver to be connected to an external transmission path and an interface processing unit connected to the transceiver. The interface processing unit comprises a serializer/deserializer circuit, an encoder/decoder, a protocol processing unit having at least two kinds of selectable protocol processing functions, and a communicate mode switch circuit for changing reference clock to be supplied to the serializer/deserializer circuit in conjunction with switching of the protocol processing function from one to another.

Claims (58)

1. An interface module for connecting a computer system element to a first external transmission path and a second external transmission path, comprising:

a first signal transceiver to be connected to said first external transmission path;

a second signal transceiver to be connected to said second external transmission path;

an interface processing unit; and

a selector for selectively connecting one of said serial signal transceivers to said interface processing unit,

wherein said interface processing unit comprises:

a serializer/deserializer circuit to convert serial signals received from said serial signal transceivers into parallel signals, convert parallel signals to be transmitted to said external transmission paths into serial signals and output the serial signals to one of said serial signal transceivers;

an encoder/decoder connected to said serializer/deserializer circuit; and

a protocol processing unit which is connected to said encoder/decoder for selectively performing at least two kinds of protocol processing,

wherein said selector selects one of said serial signal transceivers to be connected to said interface processing unit based on a given instruction issued from said computer system element,

wherein said interface unit switches reference clock to be supplied to said serializer/deserializer circuit from one to another based on said given instruction,

wherein said computer system element is a first storage control unit, said first signal transceiver is connected to a host unit via said first external transmission path, and said second signal transceiver is connected to a second storage control unit via said second external transmission path,

wherein said given instruction is issued so that said first storage control unit is connected to one of said host unit and second storage control unit in a time division manner, and

wherein said protocol processing unit further comprises:

a first protocol processing part for Fibre Channel; and

a second protocol processing part for Gigabit Ethernet,

wherein, if said given instruction specifies protocol processing for the Fibre Channel, said selector selects said first serial signal transceiver for transmitting and receiving packets according to the Fibre Channel protocol and said interface processing unit directs said protocol processing unit to select said first protocol processing part and supplies a clock with 106.25 MHz to said serializer/deserializer circuit,

if said given instruction specifies protocol processing for the Gigabit Ethernet, said selector selects said second serial signal transceiver for transmitting and receiving packets according to the Gigabit Ethernet protocol and said interface processing unit directs said protocol processing unit to select said second protocol processing part and supplies a clock with 125 MHz to said serializer/deserializer circuit.

2. A storage system, comprising:

a plurality of interface modules for connection to a plurality of external devices;

a storage control unit connected to said plurality of interface modules; and

at least one storage device connected to said storage control unit,

wherein at least one of said plurality of interface modules comprises:

a first serial signal transceiver to be connected to a first external device via a first transmission path; and

a second serial signal transceiver to be connected to a second external device via a second transmission path;

an interface processing unit; and

a selector for selectively connecting one of said first and second serial signal transceivers,

wherein said interface processing unit comprises:

a serializer/deserializer circuit to convert serial signals received from one of said first and second serial signal transceivers into parallel signals, convert parallel signals to be transmitted to one of said first and second external devices into serial signals and output the serial signals to one of said first and second transceivers;

an encoder/decoder connected to said serializer/deserializer circuit, and

a protocol processing unit connected to said encoder/decoder for selectively performing at least two kinds of protocol processing,

wherein said interface processing unit switches reference clock to be supplied to said serializer/deserializer circuit from one to another and switches the kind of protocol processing to be performed by said protocol processing unit from one to another based on an instruction issued from said storage control unit, and

wherein said protocol processing unit further comprises:

a first protocol processing part for Fibre Channel; and

a second protocol processing part for Gigabit Ethernet,

wherein, if the instruction of said storage control unit specifies protocol processing for the Fibre Channel, said interface processing unit directs said protocol processing unit to select said first protocol processing part and supplies a clock with 106.25 MHz to said serializer/deserializer circuit,

if the instruction of said storage control unit specifies protocol processing for the Gigabit Ethernet, said interface processing unit directs said protocol processing unit to select said second protocol processing part and supplies a clock with 125 MHz to said serializer/deserializer circuit.

3. The storage system according to claim 2 , wherein

said storage control unit has a memory storing communicate mode setting information, and

said storage control unit generates said instruction according to said communicate mode setting information.

4. A computer system, comprising:

a computer;

a storage system communicating with said computer through a transmission path; and

a management console connected to said computer and said storage system,

wherein each of said computer and said storage system has ate least one interface module which is comprised of:

a serial signal transceiver connected to said transmission path; and

an interface processing unit connected to said serial signal transceiver,

wherein said interface processing unit comprises:

a serializer/deserializer circuit to convert serial signals received from said serial signal transceiver into parallel signals, convert parallel signals to be transmitted to said transmission path into serial signals and output the serial signals to said transceiver;

an encoder/decoder connected to said serializer/deserializer circuit, and

a protocol processing unit connected to said encoder/decoder for selectively performing at least two kinds of protocol processing,

wherein each of the interface processing units of both said computer and said storage system switches reference clock to be supplied to said serializer/deserializer circuit from one to another and switches the kind of protocol processing to be performed by said protocol processing unit from one to another in accordance with a control signal generated by said computer or said storage system in response to an instruction from said management console,

wherein the instruction is issued by said management console so as to optimize the protocol of said transmission path in accordance with the kind of operating system running on said computer, and

wherein said protocol processing unit further comprises:

a first protocol processing part for Fibre Channel; and

a second protocol processing part for Gigabit Ethernet,

wherein, if the instruction from said management console specifies protocol processing for the Fibre Channel, said interface processing unit directs said protocol processing unit to select said first protocol processing part and supplies a clock with 106.25 MHz to said serializer/deserializer circuit,

if the instruction from said management console specifies protocol processing for the Gigabit Ethernet, said interface processing unit directs said protocol processing unit to select said second protocol processing part and supplies a clock with 125 MHz to said serializer/deserializer circuit.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT NUMBERS 10342096;10671117; 10716375; 10716376;10795407;10795408; AND 10827591 PREVIOUSLY RECORDED AT REEL: 58314 FRAME: 657. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 29, 2024
From: RAKUTEN, INC.
To: RAKUTEN GROUP, INC.
Reel/Frame 068066/0103 →
CHANGE OF NAME Recorded Dec 6, 2021
From: RAKUTEN, INC.
To: RAKUTEN GROUP, INC.
Reel/Frame 058314/0657 →
CHANGE OF ADDRESS Recorded Dec 17, 2015
From: RAKUTEN, INC.
To: RAKUTEN, INC.
Reel/Frame 037751/0006 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2014
From: GLOBAL D, LLC.
To: RAKUTEN, INC.
Reel/Frame 032503/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2014
From: HITACHI, LTD.
To: GLOBAL D, LLC
Reel/Frame 032446/0285 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2008
From: MIZUNO, MAKIO; FUJIBAYASHI, AKIRA
To: HITACHI, LTD.
Reel/Frame 020787/0393 →