Semiconductor memory device including an SOI substrate
View Patent ↗A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.
1. A semiconductor memory device comprising a plurality of MOS capacitors,
wherein said plurality of MOS capacitors are formed on an SOI substrate,
each of said plurality of MOS capacitors including a source region, a drain region connected to said source region, and a body region located between said source region and said drain region,
wherein the body region of at least one MOS capacitor of said plurality of MOS capacitors is connected to its source region.
2. A semiconductor memory device comprising a memory cell array including a plurality of first MOS transistors and a peripheral circuit including a plurality of second MOS transistors,
wherein said memory cell array and said peripheral circuit are formed on an SOI substrate,
wherein the sources region and the drain regions of said plurality of first MOS transistors are in contact with an insulation layer in said SOI substrate.