IP Library Granted Patent US 7,525,527
Granted Patent B2
US 7,525,527 · App. 10/900,187 · Granted Apr 28, 2009

Method for driving a liquid crystal display device

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Quick Facts
Patent No.
US 7,525,527
App. No.
10/900,187
Granted
Apr 28, 2009
Kind
B2
Abstract

In a liquid crystal display device, a pixel matrix is divided into a plurality of pixel regions in unit of pixel column. The pixel matrix is driven so that video signals having the same polarity are written into every divided pixel regions and video signals having different polarities are written into adjacent pixel regions during a vertical period during which signals of one screen are written and the polarity of the video signals is alternately changed every vertical period.

Claims (22)

1. A method for driving a liquid crystal display device which comprises a first substrate and a second substrate opposing the first substrate and having a common electrode so as to sandwich the liquid crystal;

the first substrate comprising:

a plurality of data lines and a plurality of gate lines arrayed crosswise; and

a pixel matrix having a plurality of pixels, each being disposed at each of intersections between said data lines and said gate lines, each pixel having a pixel transistor and a pixel capacitor;

said pixel being driven by said gate line arranged common for each pixel row, and the data line arranged common to each pixel column;

wherein said driving method comprises:

in one vertical period during which signals of one frame are written into said pixel matrix,

selecting a gate line per one horizontal period during which signals of one pixel row of the pixel matrix are written; and

writing video signals supplied to said data lines into the pixels of one pixel row connected said selected gate line;

said selecting said gate line(s) is performed by:

dividing the pixel matrix into a plurality of units of a plurality of gate lines; and

selecting said gate lines in timely adjacent (contiguous) vertical periods so as to be included in different divided pixel regions;

said data lines are driven such that polarities of the video signals supplied to any one of said data lines relative to a potential of the common electrode are different from one horizontal period to another timely adjacent (contiguous) ones; and

in said one vertical period, the polarities of the image signals written into all the pixels in each of said divided pixel regions relative to the potential of said common electrode are the same.

2. The method according to claim 1 , wherein each of said pixel regions has equal or substantially equal number of gate lines.

3. The method according to claim 1 , wherein the number of said divided pixel regions is an even number.

4. The method according to claim 1 , wherein numbers are assigned to the pixel regions and to the pixel row in the pixel region, from the position nearest to one of side edges of the liquid crystal display device, said side edges being parallel with a longitudinal direction of the gate line; and

writing of signals into all pixels in said pixel matrix is conducted by repeating steps of writing of signals into the first pixel rows of the first to n-th pixel regions by writing signals into the first pixel row in the first pixel region, thereafter writing signals into the first row in the second pixel region and so on until writing of signals into the first pixel row in n-th pixel region; and subsequently writing signals into i-th pixel row of the first to n-th pixel regions by writing signals into i-th pixel row in the first pixel region, thereafter writing i-th pixel row in the second pixel region and so on until writing of signals into i-th pixel row in n-th pixel regions, wherein i is incremented from 2 to k which is the number of pixel columns in pixel regions.

5. The method according to claim 1 , wherein said vertical period during which signals are once written into all pixels of said pixel matrix is 8.34 ms or less.

6. The method according to claim 1 , wherein a predetermined voltage is written to the data line per one horizontal period during which signals of one pixel row of the pixel matrix are written.

7. The method according to claim 1 , wherein each pixel includes a set of a pixel transistor, a pixel capacitor and a storage capacitor;

said pixel transistor having a gate terminal thereof connected to said gate line arranged common for each pixel row, having a source terminal thereof connected to the data line arranged common to each pixel column, and having a drain electrode thereof connected to the pixel capacitor and the storage capacitor of the pixel associated with said pixel transistor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2023
From: GOLD CHARM LIMITED
To: HANNSTAR DISPLAY CORPORATION
Reel/Frame 063321/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2013
From: NEC CORPORATION
To: GOLD CHARM LIMITED
Reel/Frame 030023/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2004
From: SEKINE, HIROYUKI
To: NEC CORPORATION
Reel/Frame 015628/0910 →