IP Library Patent Application 10900500
Patent Application
App. No. 10/900,500

Digital-to-analog converter with level control

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Quick Facts
Patent No.
US None
App. No.
10/900,500
Abstract

Methods and apparatus are described for converting a digital data stream to an analog signal. Charge is added to and subtracted from an input of an integrator in a manner representative of the digital data stream thereby generating the analog signal at an output of the integrator. The amount of charge is varied thereby controlling the output level of the analog signal.

Claims (26)

1 . A method for converting a digital data stream to an analog signal, comprising:

adding and subtracting an amount of charge to and from an input of an integrator in a manner representative of the digital data stream thereby generating the analog signal at an output of the integrator, the amount of charge corresponding to an output level of the analog signal; and

varying the amount of charge thereby controlling the output level of the analog signal.

2 . The method of claim 1 wherein adding and subtracting the amount of charge to and from the input of the integrator is accomplished with at least one switched capacitor circuit.

3 . The method of claim 2 wherein varying the amount of charge comprises varying a capacitance associated with the at least one switched capacitor circuit, the capacitance being for storing the amount of charge.

4 . The method of claim 3 wherein the at least one switched capacitor circuit comprises a plurality of switched capacitor circuits, each switched capacitor circuit having a unique value of the capacitance associated therewith, only one of the switched capacitor circuits adding and subtracting the amount of charge at a time.

5 . The method of claim 3 wherein varying the capacitance comprises selecting from among a plurality of capacitors.

6 . The method of claim 2 wherein varying the amount of charge comprises varying a reference voltage associated with the at least one switched capacitor circuit, the reference voltage being for charging up a capacitance with the amount of charge.

7 . The method of claim 6 wherein varying the reference voltage comprises selecting from a plurality of reference voltages.

8 . The method of claim 2 wherein operation of the switched capacitor circuit is controlled by a clock signal characterized by a frequency, and wherein varying the amount of charge comprises varying the frequency of the clock signal.

9 . The method of claim 8 wherein varying the frequency comprises selecting from among a plurality of frequencies.

10 . The method of claim 2 wherein varying the amount of charge comprises any combination of varying a capacitance associated with the at least one switched capacitor circuit, varying a reference voltage associated with the at least one switched capacitor circuit, and varying a frequency of a clock signal controlling operation of the at least one switched capacitor circuit.

11 . A digital-to-analog converter (DAC) comprising an integrator and at least one switched capacitor circuit operable to add and subtract an amount of charge to an input of the integrator in a manner representative of a digital data stream, the switched capacitor circuit further being operable to alternately employ each of a plurality of different capacitance values to accumulate the amount of charge, each of the different capacitance values resulting in a different value for the amount of charge, and therefore a different output level of the integrator.

12 . The DAC of claim 11 wherein the at least one switched capacitor circuit comprises a plurality of switched capacitor circuits each comprising at least one capacitor corresponding to one of the different capacitance values, only one of the switched capacitor circuits being operable to add and subtract the amount of charge at a time.

13 . The DAC of claim 11 wherein the at least one switched capacitor circuit comprises one switched capacitor circuit having at least one variable capacitor which may be adjusted to the different capacitance values.

14 . The DAC of claim 11 wherein the at least one switched capacitor circuit is further operable to vary a reference voltage associated with the at least one switched capacitor circuit to further vary the output level of the integrator.

15 . The DAC of claim 11 wherein the at least one switched capacitor circuit is further operable to vary a frequency of a clock signal controlling operation of the at least one switched capacitor circuit to further vary the output level of the integrator.

16 . An audio amplifier comprising the DAC of claim 11 wherein an output volume of the audio amplifier corresponds to the output level of the integrator.

17 . A digital-to-analog converter (DAC) comprising an integrator and a switched capacitor circuit operable to add and subtract an amount of charge to the integrator in a manner representative of a digital data stream, the switched capacitor circuit further being operable to alternately employ one of a plurality of different reference voltages to accumulate the amount of charge, each of the plurality of reference voltages resulting in a different value for the amount of charge, and therefore a different output level of the integrator.

18 . The DAC of claim 17 wherein the switched capacitor circuit is further operable to vary a capacitance associated with the switched capacitor circuit to further vary the output level of the integrator.

19 . The DAC of claim 17 wherein the switched capacitor circuit is further operable to vary a frequency of a clock signal controlling operation of the switched capacitor circuit to further vary the output level of the integrator.

20 . An audio amplifier comprising the DAC of claim 17 wherein an output volume of the audio amplifier corresponds to the output level of the integrator.

21 . A digital-to-analog converter (DAC) comprising an integrator and a switched capacitor circuit operable to add and subtract an amount of charge to the integrator in a manner representative of a digital data stream, the switched capacitor circuit further being operable to alternately employ one of a plurality of clock signals having different frequencies to accumulate the amount of charge, each of the plurality of clock signals resulting in a different value for the amount of charge, and therefore a different output level of the integrator.

22 . The DAC of claim 21 wherein the switched capacitor circuit is further operable to vary a capacitance associated with the switched capacitor circuit to further vary the output level of the integrator.

23 . The DAC of claim 21 wherein the switched capacitor circuit is further operable to vary a reference voltage associated with the switched capacitor circuit to further vary the output level of the integrator.

24 . An audio amplifier comprising the DAC of claim 21 wherein an output volume of the audio amplifier corresponds to the output level of the integrator.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2007
From: ENABLE GROWTH PARTNERS, LP
To: TRIPATH TECHNOLOGY INC.
Reel/Frame 019477/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2007
From: TRIPATH TECHNOLOGY INC.
To: ENABLE GROWTH PARTNERS, LP
Reel/Frame 018757/0049 →
SECURITY AGREEMENT Recorded Dec 13, 2005
From: TRIPATH TECHNOLOGY INC.
To: ENABLE GROWTH PARTNERS, LP
Reel/Frame 016883/0667 →
ASSIGNMENT OF RIGHTS UNDER FILINGS IN THE UNITED STATES PATENT AND TRADEMARK OFFICE Recorded Dec 12, 2005
From: ENABLE CAPITAL MANAGEMENT, LLC
To: ENABLE GROWTH PARTNERS, LP
Reel/Frame 016871/0780 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2004
From: PIRJABERI, MOHAMMAD; TRIPATHI, ADYA
To: TRIPATH TECHNOLOGY, INC.
Reel/Frame 015633/0836 →