Powergating method and apparatus
View Patent ↗A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.
1. A powergating circuit comprising:
a P-channel transistor having a source coupled to a first voltage source, a gate for receiving a first control signal, and a drain forming a first gated node;
an N-channel transistor having a source coupled to a second voltage source, a gate for receiving a second control signal, and a drain forming a second gated node;
a controlled circuit having a first power node coupled to the first gated node and a second power node coupled to the second gated node;
a first inverter having an input and an output for providing the first control signal;
a second inverter having an input and an output for providing the second control signal; and
means for forcing the inputs of the first and second inverters to a mid-point reference voltage during a standby mode.
2. The powergating circuit of claim 1 wherein the first control signal is boosted above the level of the first voltage source during the standby mode.
3. The powergating circuit of claim 1 wherein the second control signal is boosted below the level of the second voltage source during the standby mode.
4. The powergating circuit of claim 1 wherein the controlled circuit comprises a sense amplifier.
5. The powergating circuit of claim 1 wherein the forcing means comprises:
a third inverter having an output coupled to the input of the first inverter and having power terminals selectively coupled to the mid-point reference voltage; and
a fourth inverter having an output coupled to the input of the third inverter and having power terminals selectively coupled to the mid-point reference voltage.
6. The powergating circuit of claim 1 wherein the mid-point reference voltage comprises a bit line reference voltage.