Integrated circuit having features to limit substrate current
View Patent ↗A technique includes forming a first well in a substrate and forming a second well in the substrate. The first well is electrically isolated from the second well. The technique includes forming an element in the second well to limit current between the first well and the substrate.
1. An integrated circuit comprising:
a substrate
a first well formed in the substrate;
a second well formed in the substrate and electrically isolated from the first well;
a bypass capacitor located in the second well to be directly connected between a first power supply that provides power to circuit components and that is coupled to the first well and ground to limit a current between the first well and the substrate.
2. The integrated circuit of claim 1 , wherein a second power supply separate from the first power supply is coupled to the second well.
3. The integrated circuit of claim 2 , wherein the second power supply has significantly less noise than the first power supply.
4. The integrated circuit of claim 2 , wherein the second well is not coupled to the first power supply voltage.
5. The integrated circuit of claim 1 , wherein the first well comprises a deep n-well.
6. The integrated circuit of claim 1 , wherein the second well comprises a deep n-well.
7. The integrated circuit of claim 1 , wherein:
the first well comprises a deep n-well; and
the second well comprises a deep n-well.
8. An integrated circuit comprising:
a substrate;
a first well formed in the substrate and comprising circuitry powered by a first supply voltage;
a second well formed in the substrate and electrically isolated from the first well, the second well being coupled to a second supply voltage which is not coupled to the circuitry of the first well; and
an element located in the second well to limit a current between the first well and the substrate.
9. The integrated circuit of claim 8 , further comprising:
an isolation circuit to isolate noise present on the first supply voltage from the second supply voltage.
10. The integrated circuit of claim 9 , wherein the isolation circuit comprises a power supply.
11. The integrated circuit of claim 9 , wherein the isolation circuit is adapted to suppress radio frequency energy generated by the circuitry of the first well from propagating to the second supply voltage.
12. The integrated circuit of claim 8 , wherein the element comprises a capacitor coupled between the first supply voltage and ground.
13. The integrated circuit of claim 8 , wherein the first well comprises a deep n-well.
14. The integrated circuit of claim 8 , wherein the second well comprises a deep n-well.
15. The integrated circuit of claim 8 , wherein the second n-well contains no circuitry that receives the first supply voltage.