Method and apparatus for performing variable word width searches in a content addressable memory
View Patent ↗A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.
1. A content addressable memory (CAM) for performing search operations on variable width search data, said CAM comprising:
a) a plurality of arrays of CAM cells, coupled to a respective sub-search data bus, the sub-search data buses being combined to form a main search data bus for receiving said search data;
b) combining circuits connected to match lines and receiving at least two match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison operation performed in the associated CAM array; and
c) a selector circuit being responsive to a mode selection signal for selecting one or more output signals from the combining circuits to be switched to a processing circuit.
2. A CAM as defined in claim 1 , including a latch coupled to each match line to latch its corresponding match line signal.
3. A CAM as defined in claim 1 , wherein said processing circuit comprises a priority address encoder and multiple match resolver.
4. A method for performing variable word width searching in a content addressable memory, said method comprising the steps of:
(a) selectively combining match line latch outputs from two adjacent CAM memory arrays; and
(b) providing the selectively combined match line outputs to a processing circuit in response to a variable word width control signal, such that in a first mode the processing circuit will simultaneously receive and process four separate match line latch outputs in adjacent arrays and in a second mode a combination of two match line latch outputs are provided from two adjacent arrays to the processing circuit.
5. A method as defined in claim 4 , wherein said first mode comprises a 72-bit search.
6. A method as defined in claim 4 , wherein said second mode comprises a 144-bit search.
7. A method as defined in claim 4 , further comprising a third mode for combining four match line latch outputs and providing said combination of four match line latch outputs to the processing circuit.
8. A method as defined in claim 7 , wherein said third mode comprises 288-bit search.
9. A method as defined in claim 5 , wherein said first mode comprises a single width search.
10. A method as defined in claim 5 , wherein said second mode comprises a double width search.
11. A method as defined in claim 7 , wherein said third mode comprises a quadruple width search.