In situ doped embedded sige extension and source/drain for enhanced PFET performance
View Patent ↗Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
1. An integrated circuit transistor structure comprising:
a substrate;
an N-type transistor having an N-type gate stack on said substrate and N-type source and drain region extension and source/drain regions in said substrate adjacent said N-type gate stack;
a P-type transistor having a P-type gate stack on said substrate and P-type source and drain region extension and source/drain regions in said substrate adjacent said P-type gate stack;
wherein said P-type source and drain region extension and source/drain regions partially include a boron doped strained silicon germanium, wherein said P-type source and drain region extension extends along and under said strained silicon germanium, and
wherein said strained silicon germanium comprises two portions, wherein a top portion of said strained silicon germanium extends under said P-type gate stack more than a bottom portion of said strained silicon germanium.
2. The structure in claim 1 , further comprising a channel region in said substrate below said P-type gate stack, wherein said strained silicon germanium creates longitudinal stress on said channel region of P-type transistor.
3. The structure in claim 2 , where said strained silicon germanium is separated from said channel region of said P-type transistor.
4. The structure in claim 1 , where germanium concentration in said strained silicon germanium is between about 10% and 50%.
5. The structure in claim 1 , where boron concentration in said strained silicon germanium is more than about 1×10 20 /cm 3 .
6. The structure in claim 1 , wherein said strained silicon germanium is in-situ doped with said boron.
7. The structure in claim 1 , wherein said strained silicon germanium extends above the top of said substrate.
8. An integrated circuit transistor structure comprising:
a substrate;
an first-type transistor having an first-type gate stack on said substrate and first-type source and drain extension and source/drain regions in said substrate adjacent said first-type gate stack;
a second-type transistor having a second-type gate stack on said substrate and second-type source and drain region extension and source/drain regions in said substrate adjacent said second-type gate stack;
wherein said second-type source and drain region extension and source/drain regions partially include strained silicon, wherein said second-type extension extends alone and under said strained silicon germanium, and
wherein said strained silicon comprises two portions, wherein a top portion of said strained silicon extends under said second-type gate stack more than a bottom portion of said strained silicon.
9. The structure in claim 8 , further comprising a channel region in said substrate below said second-type gate stack, wherein said strained silicon creates longitudinal stress on said channel region of second-type transistor.
10. The structure in claim 9 , where said strained silicon is separated from said channel region of said second-type transistor.
11. The structure in claim 8 , where germanium concentration in said strained silicon is between about 10% and 50%.
12. The structure in claim 8 , where boron concentration in said strained silicon is more than about 1×10 20 /cm 3 .
13. The structure in claim 8 , wherein said strained silicon is in-situ doped with an impurity.
14. The structure in claim 8 , wherein said strained silicon extends above the top of said substrate.
15. An integrated circuit transistor structure comprising:
a substrate;
an N-type transistor having an N-type gate stack on said substrate and N-type source and drain region extension and source/drain regions in said substrate adjacent said N-type gate stack;
a P-type transistor having a P-type gate stack on said substrate and P-type source and drain region extension and source/drain regions in said substrate adjacent said P-type gate stack;
wherein said P-type source and drain region extension and source/drain regions partially include a boron doped strained silicon germanium, wherein said P-type source and drain region extension extends along and under said strained silicon germanium, and
wherein said strained silicon germanium comprises two portions, wherein a top portion of said strained silicon germanium extends under said P-type gate stack more than a bottom portion of said strained silicon germanium and wherein said silicon germanium top portion extends above a top surface of said substrate.
16. The structure in claim 15 , further comprising a channel region in said substrate below said P-type gate stack, wherein said strained silicon germanium creates longitudinal stress on said channel region of P-type transistor.
17. The structure in claim 16 , where said strained silicon germanium is separated from said channel region of said P-type transistor.
18. The structure in claim 15 , where germanium concentration in said strained silicon germanium is between about 10% and 50%.
19. The structure in claim 15 , where boron concentration in said strained silicon germanium is more than about 1×10 20 /cm 3 .
20. The structure in claim 15 , wherein said strained silicon germanium is in-situ doped with said boron.
21. The structure in claim 15 , wherein said strained silicon germanium extends above the top of said substrate.
22. An integrated circuit transistor structure comprising:
a substrate;
an first-type transistor having an first-type gate stack on said substrate and first-type source and drain region extension and source/drain regions in said substrate adjacent said first-type gate stack;
a second-type transistor having a second-type gate stack on said substrate and second-type source and drain region extension and source/drain regions in said substrate adjacent said second-type gate stack;
wherein said second-type source and drain region extension and source/drain regions partially include strained silicon, wherein said second-type source and drain region extension extends along and under said strained silicon germanium, and
wherein said strained silicon comprises two portions, wherein a top portion of said strained silicon extends under said second-type gate stack more than a bottom portion of said strained silicon and wherein said silicon germanium top portion extends above a top surface of said substrate.
23. The structure in claim 22 , further comprising a channel region in said substrate below said second-type gate stack, wherein said strained silicon creates longitudinal stress on said channel region of second-type transistor.
24. The structure in claim 23 , where said strained silicon is separated from said channel region of said second-type transistor.
25. The structure in claim 22 , where germanium concentration in said strained silicon is between about 10% and 50%.
26. The structure in claim 22 , where boron concentration in said strained silicon is more than about 1×10 20 /cm 3 .
27. The structure in claim 22 , wherein said strained silicon is in-situ doped with an impurity.
28. The structure in claim 22 , wherein said strained silicon extends above the top of said substrate.