Multiple layer and crystal plane orientation semiconductor substrate

1. A substrate, comprising:

a first crystalline semiconductor layer and a second crystalline semiconductor layer; and

an insulating layer bonding a bottom surface of said first crystalline semiconductor layer to a top surface of said second crystalline semiconductor layer, a first crystal direction of said first crystalline semiconductor layer aligned relative to a second crystal direction of said second crystalline semiconductor layer, said first crystal direction different from said second crystal direction;

a first notch formed in an edge of said first crystalline semiconductor layer at an intersection of a line along said first crystal direction and passing through a center of said first crystalline semiconductor layer and a perimeter of said first crystalline semiconductor layer;

a second notch formed in an edge of said second crystalline semiconductor layer at an intersection of a line along said second crystal direction and passing through a center of said second crystalline semiconductor layer and a perimeter of said second crystalline semiconductor layer, and

wherein said first crystalline semiconductor layer has a thickness of between about 10 nm to about 100 nm, said insulating layer has a thickness of between about 5 nm to about 500 nm and said second crystalline semiconductor layer has a thickness of greater than about 700 microns.

2. The substrate of claim 1 , wherein said first and second crystalline semiconductor layers each comprise silicon.

3. The substrate of claim 1 , wherein said first and second crystal directions are co-aligned.

4. The substrate of claim 3 , wherein first and second crystalline semiconductors each comprise {100} silicon and said first crystal direction is a [100] direction and said second crystal direction is a [110] direction.

5. The substrate of claim 1 , wherein inversion carriers have a higher mobility in said first crystal direction than any other direction in said first crystalline semiconductor layer and a crystal plane perpendicular to said second crystal direction is more easily cleaved than any other crystal plane perpendicular to any other crystal direction in said second crystalline semiconductor layer.

6. The substrate of claim 1 , wherein said insulating layer comprises silicon oxide.

7. The substrate of claim 1 , wherein said first crystalline semiconductor layer has a thickness of less than about 20 nm.

8. The substrate of claim 1 , wherein said insulating layer has a thickness of less than about 140 nm.

9. The substrate of claim 1 , wherein said first and second crystalline semiconductor layers independently comprise GaAs, GaP, GaSb, InP, InAs or InSb.

10. The substrate of claim 1 , wherein said first crystalline semiconductor layer comprise GaAs, GaP, GaSb, InP, InAs or InSb and said second crystalline semiconductor layer comprises silicon.

11. A substrate comprising:

a first crystalline semiconductor layer and a second crystalline semiconductor layer; and

an insulating layer bonding a bottom surface of said first crystalline semiconductor layer to a top surface of said second crystalline semiconductor layer, a first crystal direction of said first crystalline semiconductor layer aligned relative to a second crystal direction of said second crystalline semiconductor layer, said first crystal direction different from said second crystal direction;

a first notch formed in an edge of said first crystalline semiconductor layer at an intersection of a line along said first crystal direction and passing through a center of said first crystalline semiconductor layer and a perimeter of said first crystalline semiconductor layer; and

a second notch formed in an edge of said second crystalline semiconductor layer at an intersection of a line along said second crystal direction and passing through a center of said second crystalline semiconductor layer and a perimeter of said second crystalline semiconductor layer.