Display controller and associated method
View Patent ↗A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-playing device. The control circuit can store the control parameters via the FIFO to the memory first, and then transfer the control parameters stored in the memory via the FIFO to the register during a synchronizing blank period.
1. A display controller comprising:
a display control register, coupled to a video display device, for storing a plurality of control parameters;
a first-in-first-out buffer (FIFO) for storing data; and
a control circuit coupled to the display control register and the FIFO for accessing a memory, the control circuit comprising:
a multiplexer, comprising:
a first input end coupled to the memory:
a second input end coupled to a microcontroller unit (MCU): and
an output end coupled to the FIFO: and
a demultiplexer, comprising:
a first output end coupled to the display control register;
a second output end coupled to the memory: and
an input end coupled to the FIFO;
wherein the control circuit is capable of storing the control parameters via the FIFO to the memory, and then transferring the control parameters stored in the memory via the FIFO to the display control register during a synchronizing blank period.
2. The display controller of claim 1 , wherein the memory is an external memory.
3. The display controller of claim 2 , wherein the external memory is a DRAM.
4. The display controller of claim 2 , wherein the multiplexer further comprises a first control end and the demultiplexer further comprises a second control end, through both of which data transmission paths of the multiplexer and the demultiplexer are capable of being changed, and the MCU is therefore capable of storing the control parameters to the external memory via the multiplexer, the FIFO, and the demultiplexer sequentially.
5. The display controller of claim 2 , wherein the multiplexer further comprises a first control end and the demultiplexer further comprises a second control end, through both of which data transmission paths of the multiplexer and the demultiplexer are capable of being changed, and the external memory is therefore capable of writing the control parameters to the display control register via the multiplexer, the FIFO, and the demultiplexer during the synchronizing blank period.
6. The display controller of claim 5 , wherein the synchronizing blank period associates with a vertical synchronizing signal.
7. The display controller of claim 5 , wherein the synchronizing blank period associates with a horizontal synchronizing signal.
8. The display controller of claim 1 , wherein the MCU is a 8051 microcontroller unit.
9. The display controller of claim 1 , wherein the MCU transfers the control parameters to the control circuit via a data bus.
10. The display controller of claim 1 , wherein the MCU transfers the control parameters to the control circuit via an I 2 C bus.