Method of fabricating nano-scale resistance cross-point memory array

1. A method of fabricating a nano-scale resistance cross-point memory array, comprising:

preparing a silicon substrate;

depositing silicon oxide on the substrate to a predetermined thickness;

forming spaced-apart, nano-scale trenches extending in a first direction in the silicon oxide;

depositing a first connection line in the spaced-apart, nano-scale trenches;

depositing a memory resistor layer in the spaced-apart, nano-scale trenches on the first connection line;

depositing another silicon oxide layer;

forming spaced-apart, nano-scale trenches extending in a second direction in the other silicon oxide layer;

depositing a second connection line in the spaced-apart, nano-scale trenches extending in the second direction on the memory resistor layer; and

completing the memory array.

2. The method of claim 1 wherein said forming a spaced-apart, nano-scale trenches in the first direction further includes:

depositing a hard mask on the oxide;

depositing a silicon nitride cap on the hard mask;

patterning and etching the silicon nitride cap, hard mask and oxide;

depositing a second silicon nitride layer and etching the second silicon nitride layer to form a silicon nitride spacer;

depositing a second oxide layer;

chemical mechanical polishing the structure;

selectively etching the structure to remove oxide equal to the thickness of the hard mask and the silicon nitride cap;

depositing a second hard mask layer; and

chemically mechanically polishing the second hard mask to form the spaced-apart, nano-scale trenches.

3. The method of claim 1 wherein said depositing a first connection line includes depositing an electrode material taken from the group of electrode materials consisting of Y x Ba 2 Cu 3 O 7-x , Pt and Ir.

4. The method of claim 1 wherein said depositing a memory resistance layer includes depositing a layer of Pr 0.7 Ca 0.3 MnO 3 .

5. The method of claim 1 wherein said depositing a second connection line includes depositing an electrode material taken from the group of electrode materials consisting of Al, Cu, Pt, Ir and Au.

6. The method of claim 1 wherein the fabrication includes forming a memory array having an average memory bit area equal to 1 F 2 , where F is the minimum resolution width of the lithographic tool.

7. The method of claim 1 , which includes, after said forming spaced-apart nano-scale trench in the silicon oxide, implanting ions to form an n+ layer under each spaced-apart, nano-scale trench; implanting ions to form a p+ layer under each spaced-apart, nano-scale trench; and diffusing the n+ ions to occupy between about 20% to 30% of the space between the spaced-apart, nano-scale trenches.

8. The method of claim 7 wherein said diffusing includes heating the structure to a temperature of between about 850° C. to 1000° C. for between about 10 minutes and 30 minutes.

9. The method of claim 1 which further includes, after said depositing silicon oxide, forming a silicon epitaxial layer having a thickness of between about 100 nm to 200 nm on the silicon oxide.

10. A method of fabricating a nano-scale resistance cross-point memory array, comprising:

preparing a silicon substrate;

depositing first silicon oxide layer on the substrate to a predetermined thickness;

forming spaced-apart, nano-scale trenches extending in a first direction in the silicon oxide;

depositing a first connection line in the spaced-apart, nano-scale trenches extending in the first direction, including depositing an electrode material taken from the group of electrode materials consisting of Y x Ba 2 Cu 3 O 7-x , Pt and Ir;

depositing a memory resistor layer of Pr 0.7 Ca 0.3 MnO 3 in the spaced-apart, nano-scale trenches extending in the first direction on the first connection line;

depositing another silicon oxide layer;

forming spaced-apart, nano-scale trenches extending in a second direction in the other silicon oxide layer, wherein the spaced-apart, nano-scale trenches extending in a second direction expose the memory resistor layer;

depositing a second connection line in the spaced-apart, nano-scale trenches extending in a second direction on the memory resistor layer, including depositing an electrode material taken from the group of electrode materials consisting of Al, Cu, Pt, Ir and Au.; and

completing the memory array.

11. The method of claim 10 wherein said forming spaced-apart, nano-scale trenches extending in the first direction further includes:

depositing a hard mask on the oxide;

depositing a silicon nitride cap on the hard mask;

patterning and etching the silicon nitride cap, hard mask and oxide;

depositing a second silicon nitride layer and etching the second silicon nitride layer to form a silicon nitride spacer;

depositing a second oxide layer;

chemically mechanically polishing the structure;

selectively etching the structure to remove oxide equal to the thickness of the hard mask and the silicon nitride cap;

depositing a second hard mask layer; and

chemically mechanically polishing the second hard mask to form the spaced-apart, nano-scale trenches.

12. The method of claim 11 which further includes, after depositing the memory resistor layer,

depositing a third silicon nitride layer and depositing a third silicon oxide layer;

patterning and etching the third silicon nitride layer and the third oxide layer;

depositing a fourth silicon nitride layer to from silicon nitride sidewalls on the third silicon oxide layer; and

depositing a fourth silicon oxide layer within the confines of the silicon nitride sidewalls.

13. The method of claim 12 wherein said depositing a first connection line in the spaced-apart, nano-scale trenches extending in the first direction includes depositing electrode material to a thickness of at least one-half that of the combined thickness of the combined silicon nitride layers in the structure at the time of depositing the first connection line.

14. The method of claim 12 wherein said depositing a memory resistor layer in the spaced-apart, nano-scale trenches extending in the first direction includes depositing memory resistor material to a thickness of at least one-half that of the thickness of the second silicon nitride layer.

15. The method of claim 12 wherein said depositing a second connection line in the spaced-apart, nano-scale trenches extending in the second direction includes depositing electrode material to a thickness of at least one-half that of the thickness of the third silicon nitride layer.

16. The method of claim 10 wherein the fabrication includes forming a memory array having an average memory bit area equal to 1 F 2 , where F is the minimum resolution width of the lithographic tool.

17. The method of claim 10 which includes, after said forming spaced-apart nano-scale trenches in the silicon oxide, implanting ions to form an n+ layer under each trench; implanting ions to form a p+ layer under each trench; diffusing the n+ ions to occupy between about 20% to 30% of the space between the spaced-apart trenches by heating the structure to a temperature of between about 850° C. to 1000° C. for between about 10 minutes and 30 minutes.

18. The method of claim 10 which further includes, after said depositing silicon oxide, forming a silicon epitaxial layer having a thickness of between about 100 nm to 200 nm on the silicon oxide.