Flash memory unit and method of programming a flash memory device

1. A method of programming a flash memory device from a memory unit, comprising:

applying a programming gate voltage to a control gate of the memory device;

applying a programming drain voltage to a drain of the memory device; and

coupling a source bias potential to a source of the memory device with a pass transistor controlled with a control signal having a voltage greater than an operational voltage available to the memory unit from an external power source and the control signal being the selective application of one of the programming drain voltage or the programming gate voltage to a gate of the pass transistor, wherein the voltage of the control signal is at least three times the operational voltage available to the memory unit from the external power source.

2. The method according to claim 1 , wherein coupling the source bias potential to the source of the memory device includes coupling the source bias potential to a common source junction node of a sector of the memory device.

3. The method according to claim 1 , wherein the pass transistor couples a source-voltage-source resistor to the source of the memory device.

4. The method according to claim 1 , wherein the control signal is selectively applied to the pass transistor using a logic circuit.

5. The method according to claim 1 , wherein the memory device is selected from a floating gate memory device and a charge trapping dielectric memory device.

6. A flash memory unit having a plurality of flash memory devices arranged in a sector, comprising:

a plurality of wordlines arranged with respect to a plurality of bitlines and a charge storing layer to operatively form the memory devices;

a pass transistor selectively operable in response to a control signal to couple a source bias voltage to a common source junction node defined by bitlines connected to function as source conductive regions for the memory devices during programming; and

a control circuit for selectively applying one of a programming gate voltage or a programming drain voltage to a gate of the pass transistor as the control signal, wherein the control signal has a potential of at least three times an operational voltage available to the memory unit from an external power source.

7. The memory unit according to claim 6 , wherein the charge storing layer is conductive and the memory devices are configured as floating gate memory devices.

8. The memory unit according to claim 6 , wherein the charge storing layer is non-conductive and the memory devices are configured as dielectric charge storing devices, each with plural charge storing regions.

9. The memory unit according to claim 6 , further comprising a source-voltage-source resistor connected to a source bias input node of the pass transistor.