Nonvolatile semiconductor memory device
View Patent ↗The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor. A transfer gate comprising these NMOS and PMOS transistors drives the control gate electrode (WL).
1. A nonvolatile semiconductor memory device comprising:
memory cell transistors each having a floating gate electrode and a control gate electrode (WL),
wherein the control gate electrode (WL) of the memory cell transistor takes a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential according to an operating state at the selection thereof, and
wherein a first NMOS transistor of which the source is connected to a control (/ER) for controlling a second NMOS transistor which drives the control gate electrode (WL) to the first power supply potential (VCC), the drain is connected to the gate of the second NMOS transistor, and
the gate is connected to the first power supply potential (VCC), is provided between the second NMOS transistor and the control signal (/ER), a PMOS transistor is provided in parallel with the second NMOS transistor, and
the control gate electrode (WL) is driven by a transfer gate comprising the NMOS transistor and the PMOS transistor.
2. A nonvolatile semiconductor memory device comprising:
memory cell transistors each having a floating gate electrode and a control gate electrode (WL);
a plurality of decoders (XDEC) which drive the control gate electrodes (WL);
redundant control gate electrodes (WL) replaceable when the control gate electrodes (WL) are defective;
memory means (redundant element) which stores addresses for the defective control gate electrodes (WL);
said control gate electrode (WL) of the memory cell transistor assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential according to an operating state at the selection thereof; and
a plurality of redundancy selectors (RXSEL) for activating and deactivating the decoders (XDEC), which are provided every said decoders (XDEC);
wherein the redundancy selectors (RXSEL) input signals (RA, /RA and RDDEN) held in and outputted from the memory means (redundant element).