Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.
1. A semiconductor integrated circuit device comprising:
a logic circuit including at least a first MIS transistor;
a monitoring circuit including at least a second MIS transistor to output an oscillation signal,
a substrate bias voltage generator to supply a substrate bias voltage to the first MIS transistor and the second MIS transistor; and
a comparator to compare a reference clock signal and the oscillation signal,
wherein the substrate bias voltage generator changes the substrate bias voltage on a predetermined voltage unit basis in accordance with a result of a comparison operation of the comparator.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the comparator outputs a first control signal when a delay difference of the oscillation signal from the reference clock signal is faster than a predetermined value and the comparator outputs a second control signal when the delay difference is slower than the predetermined value.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein the substrate bias voltage generator controls the substrate bias voltage so as to increase absolute threshold values of the first and second MIS transistors, when the substrate bias voltage receives the first control signal, and
wherein the substrate bias voltage generator controls the substrate bias voltage so as to decrease the absolute threshold values of the first and second MIS transistors, when the substrate bias voltage generator receives the second control signal.
4. The semiconductor integrated circuit device according to claim 3 ,
wherein the substrate bias generator includes a digital-to-analog converter and a plural stages of registers having plural register positions to the digital-to-analog converter,
wherein the digital-to-analog converter outputs the substrate bias voltage according to the register position, and
wherein the register position is changed according to whether the substrate bias generator receives the first control signal or the second control signal.
5. The semiconductor integrated circuit device according to claim 3 ,
wherein the substrate bias generator includes a first digital-to-analog converter to supply the substrate bias voltage to the second MIS transistor, a second digital-to-analog converter to supply the substrate bias voltage to the first MIS transistor and first plural stages of registers having plural first register positions to the first digital-to-analog converter,
wherein the first digital-to-analog converter outputs the substrate bias voltage to the second MIS transistor according to the first register position, and
wherein the first register position is changed according to whether the substrate bias generator receives the first control signal or the second control signal.
6. The semiconductor integrated circuit device according to claim 5 ,
wherein the second digital-to-analog converter supplies the substrate bias voltage that has the same value as the first digital-to-analog converter.
7. The semiconductor integrated circuit device according to claim 1 ,
wherein the monitoring circuit includes a plurality of inverters connected in series, and
wherein each of the plurality of inverters includes the second MIS transistor.
8. The semiconductor integrated circuit device according to claim 4 , wherein the register position is changed one by one within said plural register positions according to whether the substrate bias generator receives the first control signal or the second control signal.
9. The semiconductor integrated circuit device according to claim 5 , wherein the first register position is changed one by one within said plural first register positions according to whether the substrate bias generator receives the first control signal or the second control signal.
10. The semiconductor integrated circuit device comprising:
a logic circuit including at least a first MIS transistor, wherein subthreshold leakage current flows through the first MIS transistor; and
a control circuit to control an operating speed of the logic circuit,
wherein the control circuit changes a voltage to supply to the first MIS transistor on a predetermined voltage unit basis,
wherein the subthreshold leakage current of the first MIS transistor increases when the control circuit increases the operating speed of the logic circuit, and
wherein the subthreshold leakage current of the first MIS transistor decreases when the control circuit decreases the operating speed of the logic circuit
wherein the control circuit includes a monitoring circuit including at least a second MIS transistor to output an oscillation signal and a comparator to compare a reference clock signal and the oscillation signal, and
wherein the control circuit supplies the voltage to the first MIS transistor and the MIS second transistor, and wherein the control circuit changes the voltage on a predetermined voltage unit basis in accordance with a result of a comparison operation of the comparator.
11. The semiconductor integrated circuit device according to claim 10 ,
wherein the voltage is a substrate bias voltage, and
wherein the control circuit includes a substrate bias voltage generator to supply the substrate bias voltage to the first MIS transistor and the second MIS transistor.
12. The semiconductor integrated circuit device according to claim 11 ,
wherein the comparator outputs a first control signal when a delay difference of oscillation signal from the reference clock signal is faster than a predetermined value and the comparator outputs a second control signal when the delay difference is slower than the predetermined value.
13. The semiconductor integrated circuit device according to claim 12 ,
wherein the substrate bias voltage generator controls the substrate bias voltage so as to increase absolute threshold values of the first and second MIS transistors, when the substrate bias voltage generator receives the first control signal, and
wherein the substrate bias voltage generator controls the substrate bias voltage so as to decrease the absolute threshold values of the first and second MIS transistors, when the substrate bias voltage receives the second control signal.
14. The semiconductor integrated circuit device according to claim 13 ,
wherein the substrate bias generator includes a digital-to-analog converter and plural stages of registers having plural register positions to the digital-to-analog converter,
wherein the digital-to-analog converter outputs the substrate bias voltage according to the register position, and
wherein the register position is changed according to whether the substrate bias voltage generator receives the first control signal or the second control signal.
15. The semiconductor integrated circuit device according to claim 10 ,
wherein the monitoring circuit includes a plurality of inverters connected in series, and
wherein each of the plurality of inverters includes the second MIS transistor.
16. The method of controlling the operating speed of the logic circuit according to claim 15 ,
wherein the voltage is a substrate bias voltage.
17. The semiconductor integrated circuit device according to claim 14 , wherein the register position is changed one by one within said plural register positions according to whether the substrate bias generator receives the first control signal or the second control signal.