Reset generator circuit for generating a reset signal
View Patent ↗A reset generator circuit has an oscillator circuit and a delay circuit having a clock signal input, which is connected to an output of the oscillator circuit. The delay circuit can be activated by a control signal at a control input and is designed for outputting a first signal after a first time period and for outputting a second signal after a time period after the outputting of the first signal. The reset generator circuit comprises a generator circuit designed for outputting a reset signal in the event of detection of the first signal up to the detection of the second signal. Furthermore, the reset generator circuit contains a comparison device designed for a comparison of a supply potential with a potential threshold value and for outputting the control signal in the event of the potential threshold value being exceeded. The delay circuit and the generator circuit can be controlled by the comparison device.
1. A reset generator circuit for generating a reset signal, comprising:
an oscillator circuit configured to output a clock signal to an output thereof;
a delay circuit comprising a clock signal input connected to the output of the oscillator circuit, the delay circuit further comprising a signal output and a control input, and configured to be activated by a control signal at the control input, and output a first signal state after a first predetermined time period, and output a second signal state after a second predetermined time period after outputting the first signal state;
a generator circuit comprising a signal input coupled to the signal output of the delay circuit, and a reset signal output, and configured to be activated by the control signal at a control input thereof, and further configured to output a reset signal in the event of a detection of the first signal state at the signal input thereof until a detection of the second signal state at the signal input of the generator circuit; and
a comparison device configured to compare a supply potential with a potential threshold value and output the control signal to a signal output thereof when the supply potential exceeds the potential threshold value, wherein the signal output thereof is connected to the control input of the delay circuit and the control input of the generator circuit,
wherein the generator circuit is further configured to output a turn-off signal to a second output thereof after the detection of the second signal state at the signal input, and the second output is coupled to a control input of the oscillator circuit, wherein the oscillator circuit is turned off in response to the turn-off signal at the control input.
2. The reset generator circuit as claimed in claim 1 , wherein the generator circuit or the delay circuit comprise a specific initial operating state and are switched into the initial state by the control signal at the control input.
3. The reset generator circuit as claimed in claim 1 , wherein the generator circuit is configured to output the reset signal upon a detection of a first rising edge of a signal comprising the first signal state until a detection of a second rising edge of the signal comprising the second signal state.
4. The reset generator circuit as claimed in claim 1 , wherein the comparison device comprises a first detection circuit configured to output a switching signal to a second detection circuit thereof, wherein the second detection circuit is activated by the switching signal, wherein the first detection circuit outputs the switching signal when the supply potential exceeds a first threshold value, and wherein the second detection device is configured to output the control signal.
5. The reset generator circuit as claimed in claim 4 , wherein a tap for the switching signal is provided between the charge store and the second terminal of the second controllable path.
6. The reset generator circuit as claimed in claim 4 , wherein the second detection circuit of the comparison device comprises an inverter circuit having at least one asymmetrical inverter associated therewith, a ratio of which between a changeover point of the asymmetrical inverter and a difference between the supply potential and the reference potential is low.
7. The reset generator circuit as claimed in claim 4 , wherein the first and second detection circuits of the comparison device comprise field-effect or bipolar transistors.
8. The reset generator circuit as claimed in claim 1 , wherein the comparison device is configured to output the control signal as a differential control signal, the differential control signal comprising a first and a second logic level.
9. The reset generator circuit as claimed in claim 1 , wherein the delay circuit comprises a counting device configured to output the first signal state after a first number of clock periods of the clock signal and output the second signal state after a second number of clock periods of the clock signal.
10. The reset generator circuit as claimed in claim 1 , wherein the delay circuit comprises at least two series-connected bistable multivibrators configured to form an asynchronous binary counter.
11. The reset generator circuit as claimed in claim 1 , wherein the delay circuit comprises a frequency divider.
12. The reset generator circuit as claimed in claim 1 , wherein the oscillator circuit comprises a ring oscillator configured to output a rectangular-waveform clock signal.
13. The reset generator circuit as claimed in claim 1 , wherein the comparison device comprises at least one third detection circuit configured to detect a supply potential fluctuation, wherein the comparison device is further configured to output the control signal after a detection of a supply potential fluctuation.