IP Library Granted Patent US 7,196,368
Granted Patent B2
US 7,196,368 · App. 10/914,223 · Granted Mar 27, 2007

Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film

Assignee: Renesas Technology Corp.
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Quick Facts
Patent No.
US 7,196,368
App. No.
10/914,223
Granted
Mar 27, 2007
Kind
B2
Abstract

A capacitor consisting of a storage electrode ( 19 ), a capacitor dielectric film ( 20 ) and a plate electrode ( 21 ) is formed in a trench formed through dielectric films ( 6, 8, 10 and 12 ) stacked on a semiconductor substrate ( 1 ) and buried wiring layers ( 9 and 11 ) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers ( 9 and 11 ) for a global word line and a selector line. As the upper face of an dielectric film ( 32 ) which is in contact with the lower face of wiring ( 34 ) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor ( 33 ), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

Claims (25)

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of dielectric films stacked on a main surface of the semiconductor substrate as stacked dielectric films, at least one of the plurality of dielectric films being a silicon nitride film;

a memory cell area in which a field-effect transistor provided with a diffusion region and a conductive type of which is reverse to that of the semiconductor substrate, a gate electrode, a gate insulating film, and a capacitor are formed; and a peripheral circuit area and a first wiring formed in the peripheral circuit area, wherein:

the capacitor is formed in the memory cell area, in a concave portion of a trench which is bored into more than two dielectric films of the plurality of dielectric films including the silicon nitride film, wherein the capacitor includes a first electrode, a capacitor dielectric film, and a second electrode, wherein the first electrode is formed in a crown shape and a bottom portion of the first electrode lies at a bottom of the trench, and wherein the capacitor dielectric film is formed on an inner surface of the first electrode, on an upper portion of an outer surface of the first electrode, and includes a portion formed on a portion of an upper surface of the silicon nitride film abutting the capacitor;

a plurality of second wirings located over the stacked dielectric films in the peripheral circuit area, and one of the second wirings is connected to the first wiring by a plurality of plugs, which plugs are connected by stacking thereof; and

an upper face of the stacked dielectric films is extended from the peripheral circuit area to the memory cell area, and at least a portion of a thickness of the stacked dielectric films is in contact with a side face of the capacitor, wherein the upper surface of the stacked dielectric films extended from the memory cell area to peripheral circuit area is flat, and,

wherein an upper surface of the silicon nitride film is located higher than an upper surface of the bottom portion of the first electrode.

2. A semiconductor memory device according to claim 1 , wherein:

some of the stacked dielectric films are provided between the capacitor and the semiconductor substrate;

a first wiring layer located on one of the stacked dielectric films is separated from the capacitor; and

a second wiring layer located on one of the stacked dielectric films is formed over the capacitor.

3. A semiconductor memory device according to claim 1 , wherein the first wiring layer is selected from one of a polycrystalline silicon film containing high-concentration impurities; a stacked film of a polycrystalline silicon film and a silicide film; a stacked film of a tungsten film, a barrier metal film and a polycrystalline silicon film; and a stacked film of a tungsten film and a barrier metal film; a tungsten film; and a copper film.

4. A semiconductor memory device according to claim 1 , wherein the capacitor dielectric film is selected from one of a stacked film of an oxide film and a nitride film; a stacked film of an oxide film and a tantalum pentoxide film; a stacked film of a nitride film and a tantalum pentoxide film; and a stacked film of an oxide film, a nitride film, and a tantalum pentoxide film; a BST film; and a PZT film.

5. A semiconductor memory device according to claim 1 , wherein the second electrode is comprised of a polycrystalline silicon film containing high-concentration impurities or a refractory metal film.

6. A semiconductor memory device according to claim 1 , wherein the first electrode is electrically connected to the diffusion region of the field effect transistor formed in the memory cell area, via a conductor formed through some of the stacked dielectric films provided between the capacitor and the semiconductor substrate.

7. A semiconductor memory device according to claim 2 , wherein the first wiring layer is electrically connected to the second wiring layer, via a conductor formed through some of the stacked dielectric films.

8. A semiconductor memory device according to claim 1 , wherein an upper face of one of the stacked dielectric films is extended into the memory cell area and is in contact with a side or bottom of the capacitor, and the upper face is in contact with a lower face of a wiring layer formed in the peripheral circuit area.

9. A semiconductor memory device according to claim 1 , wherein:

the first electrode of the capacitor is provided in the concave portion; and

the capacitor dielectric film and the second electrode are extended outside from the inner face of the first electrode.

10. A semiconductor memory device according to claim 1 , wherein:

the first electrode of the capacitor is formed on an inner face of the concave portion and protruded upward from the inner face of the concave portion; and

the capacitor dielectric film and the second electrode are extended outside a protruded portion of the first electrode from the inside of the first electrode.

11. A semiconductor memory device according to claim 2 , wherein the second wiring layer is formed over the capacitor, via some of the stacked dielectric films.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
MERGER Recorded Sep 20, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025008/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2005
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 016177/0066 →
Continuity (3)
Continuation 1020621500 · Jul 29, 2002
Continuation 0907710000 · May 20, 1998
Related Publication 20050045933A1 · Mar 3, 2005