IP Library Granted Patent US 7,970,262
Granted Patent B2
US 7,970,262 · App. 10/914,808 · Granted Jun 28, 2011

Buffer descriptor structures for communication between decoder and display manager

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Quick Facts
Patent No.
US 7,970,262
App. No.
10/914,808
Granted
Jun 28, 2011
Kind
B2
Abstract

A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

Claims (13)

1. A system for providing images for display, said system comprising:

a memory for storing parameters associated with the images;

a first processor for decoding said images and writing said parameters associated with the images to the memory; and

a second processor for reading the parameters from the memory and determining an order for displaying the images based on the parameters and determining times to overwrite the particular ones of the decoded images in the memory based on the parameters that the second processor has read;

wherein the memory stores the decoded images; and

wherein reading the parameters from the memory and determining times to overwrite the particular ones of the decoded images in the memory based on the parameters that the second processor has read further comprises determining whether the next picture is an I picture or a P picture, and if the next picture is an I picture or a P picture, determining to overwrite an I picture or P picture that has been stored for the longest time in the memory.

2. The system of claim 1 , wherein the first processor overwrites the particular ones of the decoded images in the memory.

3. The system of claim 2 , wherein the second processor signals the first processor to overwrite the particular ones of the decoded images at approximately said times, and wherein the first processor overwrites the particular ones of the decoded images after the second processor signals the first processor.

4. The system of claim 1 , wherein the parameters comprises a parameter from a group parameters consisting of repeat first field and top field first.

5. The system of claim 1 , wherein the first processor provides the images for display according to the order determined by the second processor.

6. The system of claim 1 , wherein reading the parameters from the memory and determining times to overwrite the particular ones of the decoded images in the memory based on the parameters that the second processor has read further comprises determining whether the next picture is a B picture, and if the next picture is a B picture, determining when a B picture has finished display and determining to overwrite the B picture after the B picture has finished display.

7. The system of claim 6 , wherein determining when a B picture has finished display further comprises examining a 3:2 pulldown parameter by the second processor.

8. The system of claim 1 , wherein the parameters read by the second processor are parameters encoded with the pictures.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →