CMOS compatible process with different-voltage devices
View Patent ↗A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
1. A process of manufacturing different-voltage devices, comprising steps of:
providing a substrate, wherein low-voltage device regions, high-voltage device regions, and isolation regions can be formed in;
forming at least one high-voltage well in said substrate;
forming at least one N-well in said low-voltage device regions, at least one P-well in said low-voltage device regions, source/drain wells in said high-voltage device regions, and isolation wells in said isolation regions;
forming a patterned nitride layer over said substrate;
forming a field oxide layer over said isolation region;
forming a HV gate oxide layer over said high-voltage device regions;
forming an LV gate oxide layer over said low-voltage device regions and said high-voltage device regions;
forming a poly layer over said high-voltage device regions and said low-voltage device regions; and
forming PSD/NSD regions in said high-voltage device regions and said low-voltage device regions.
2. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein process parameters of forming at least one high-voltage well in a substrate are adjusted to determine a breakdown voltage thereof.
3. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein steps of forming at least one N-well in said low-voltage device region, at least one P-well in said low-voltage device region, source/drain wells in said high-voltage device region, and said isolation wells in said isolation regions comprises steps of:
forming an N-well mask over desired regions, wherein said desired regions may be said low-voltage device regions, source/drain wells in said high-voltage device regions, and isolation wells in said isolation regions;
forming a P-well mask over desired regions, wherein said desired regions may be said low-voltage device regions, source/drain wells in said high-voltage device regions, and isolation wells in said isolation regions;
implanting N-type conductive ions and P-type conductive ions to form N-wells and P-wells respectively; and
driving in said N-type conductive ions and said P-type conductive ions.
4. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein process parameters of forming wells in said low-voltage device regions and said high-voltage device regions are adjusted for implanting ions into both said high-voltage regions and said low-voltage device regions simultaneously.
5. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein said isolation wells in said isolation regions are for isolating devices formed over said low-voltage device regions from devices formed over said high-voltage device regions.
6. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein forming said HV gate oxide layer over said high-voltage device regions comprises steps of:
forming a HV gate oxide mask over said high-voltage device regions; and
forming said HV gate oxide layer over said high-voltage device regions.
7. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein a thickness of said HV gate oxide layer is thicker than a thickness of said LV gate oxide layer.
8. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein a threshold voltage of devices formed over said low-voltage device regions and said high-voltage device regions is adjusted by adjusting a thickness of said HV gate oxide layer and a thickness of said LV gate oxide layer.
9. The process of manufacturing different-voltage devices as claimed in claim 1 , wherein forming PSD/NSD regions in said low-voltage device regions and said high-voltage device regions comprises steps of:
forming a PSD/NSD mask over said low-voltage device regions and said high-voltage device region;
implanting N+ conductive ions to form a source/drain of NMOS devices and a body contact of PMOS devices;
implanting P+ conductive ions to form a source/drain of said PMOS device and a body contact of said NMOS device; and
driving in said N+ conductive ions and said P+ conductive ions.
10. The process of manufacturing different-voltage devices as claimed in claim 9 , wherein parameters of implanting N+ conductive ions are adjusted for implanting said N+ conductive ions into both said high-voltage device regions and said low-voltage device regions.
11. The process of manufacturing different-voltage devices as claimed in claim 9 , wherein parameters of implanting P+ conductive ions are adjusted for implanting said P+ conductive ions into both said high-voltage device regions and said low-voltage device regions.