Partially patterned lead frames and methods of making and using the same in semiconductor packaging
View Patent ↗A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.
1. A method of forming a plurality of electronic packages using partially patterned lead frames comprising the steps of:
providing a film having a top surface and a bottom surface;
partially patterning the film from the top surface but not entirely through to the bottom surface in a first region, leaving a second region on the film not partially patterned from the top surface, the second region forming a plurality of partially patterned lead frames, each having chip receiving area for supporting an integrated circuit (IC) chip and a plurality of electrical leads for providing electrical connections to the IC chip;
the first region forming a webbed structure interconnecting the chip receiving areas and electrical leads of each lead frame and connecting the plurality of lead frames to one another in street portions of the film;
providing a plurality of chips each having a plurality of electrical terminals for attachment to a corresponding lead frame;
attaching each chip to the chip receiving area on a corresponding lead frame;
forming an electrical connection between at least one terminal of each chip and one of the electrical leads of the lead frame;
encapsulating the lead frames by applying an encapsulant material over the lead frames and the street portions of the film;
back patterning from the bottom surface of the film the first region to remove the webbed structure and the street portions of the film; and
singulating the encapsulant material disposed over the street portions of the film to form individual chip scale packages.
2. The method according to claim 1 , wherein each chip is a semiconductor chip.
3. The method according to claim 1 , wherein the step of attaching the chip is accomplished by back-bonding the chip to a chip-pad using an epoxy resin to form an etched lead frame package (ELP).
4. The method according to claim 1 , wherein the step of forming at least one interconnection is accomplished by using wire-bonding techniques.
5. The method according to claim 1 , wherein the step of attaching the chip is accomplished by connecting the terminals on the chip to the end portions of the electrical leads extending to the chip receiving area to form an ELP with a flip-chip (ELPF).
6. The method according to claim 1 , wherein the step of forming the electrical connection is accomplished by connecting the terminals on the chip to the end portions of the electrical leads extending to the chip receiving area.
7. The method according to claim 1 , wherein the encapsulant material is a resin.
8. The method according to claim 1 , wherein each lead frame further comprises a first region having exposed vertical walls and the encapsulant material interlocks with the exposed vertical walls.
9. The method according to claim 1 , wherein the bottom surface of each package is formed with electrical connectors for connecting the electrical leads to a next level of attachment.
10. The method according to claim 1 , wherein the plurality of lead frames are laid in a matrix in a block/window pattern.
11. The method according to claim 1 , wherein the packages are chip scale packages.