I/O descriptor cache for bus mastering I/O controllers

1. An apparatus that includes an I/O descriptor cache that is accessible over a PCI bus, comprising:

an I/O descriptor cache that stores descriptors that describe data to be transferred during corresponding I/O operations on a PCI bus internal to a computer system;

one or more I/O controllers configured to control one or more I/O devices and to access I/O descriptors stored in the I/O descriptor cache without having to access a main memory, thereby conserving I/O bandwidth and power;

wherein copies of descriptors stored in the descriptor cache are not present in a main memory; and

wherein the I/O descriptor cache is located within one of the one or more I/O controllers, wherein the I/O controller can use the descriptor cache, wherein the I/O controller also functions as a PCI device that provides access to the descriptor cache to other devices via the PCI bus, and wherein the I/O controller is a Universal Serial Bus (USB) Host Controller.

2. The apparatus of claim 1 , wherein the I/O descriptor cache resides in an additional memory address space which is separate from the address space used by the main memory.

3. The apparatus of claim 2 ,

wherein the I/O descriptor cache is configured to store USB descriptors required by the USB Host Controller.

4. A computer system that includes an I/O descriptor cache that is accessible over a PCI bus, comprising:

a CPU;

a main memory;

an I/O descriptor cache that stores descriptors that describe data to be transferred during corresponding I/O operations on a PCI bus internal to a computer system;

one or more I/O controllers configured to control one or more I/O devices, and to access I/O descriptors stored in the I/O descriptor cache without having to access the main memory, thereby conserving I/O bandwidth and power;

wherein copies of descriptors stored in the descriptor cache are not present in a main memory; and

wherein the I/O descriptor cache is located within one of the one or more I/O controllers, wherein the I/O controller can use the descriptor cache, wherein the I/O controller also functions as a PCI device that provides access to the descriptor cache to other devices via the PCI bus, and wherein the I/O controller is a Universal Serial Bus (USB) Host Controller.

5. The computer system of claim 4 , wherein the I/O descriptor cache resides in an additional memory address space which is separate from the address space used by the main memory.

6. The computer system of claim 5 ,

wherein the I/O descriptor cache is configured to store USB descriptors required by the USB Host Controller.

7. A method that accesses an I/O descriptor cache, comprising: storing I/O descriptors frequently polled by one or more I/O controllers to control I/O operations in the I/O descriptor cache, wherein the I/O descriptor cache is located within one of the one or more I/O controllers, wherein the I/O controller can use the descriptor cache, wherein the I/O controller also functions as a PCI device that provides access to the descriptor cache to other devices via the PCI bus, and wherein the I/O controller is a Universal Serial Bus (USB) Host Controller; and

accessing I/O descriptors stored in the I/O descriptor cache from I/O controllers on the PCI bus without accessing a main memory, thereby conserving I/O bandwidth and power;

wherein copies of descriptors stored in the descriptor cache are not present in a main memory;

wherein the I/O operations occur across a PCI bus internal to a computer system.

8. The method of claim 7 , wherein assigning an address space to the I/O descriptor cache involves assigning an additional memory address space which is separate from the address space used by the main memory.

9. The method of claim 8 ,

wherein storing I/O descriptors in the I/O descriptor cache involves storing USB descriptors required by the USB Host Controller.