Method of fabricating a high-layer-count backplane
View Patent ↗The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.
1. A method of fabricating a multi-layer circuit board, the method comprising:
creating first and third layer arrangements, each comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of dielectric material;
creating a second layer arrangement comprising at least two patterned power plane layers, stacked between layers of a dielectric material;
laminating the first, second, and third layer arrangements together in that order, such that a reference plane layer on each side shields the second layer arrangement from the high-speed differential trace layers; and
electrically connecting the reference plane layers to each other, while leaving the power plane layers electrically isolated from each other and from the reference plane layers, within the circuit board.
2. The method of claim 1 , further comprising:
creating fourth and fifth layer arrangements, each comprising at least one low-speed trace layer;
laminating the fourth layer arrangement between the first and second layer arrangements, such that at least one reference plane separates the low-speed trace layer from the patterned power layers and at least one other reference plane separates the low-speed trace layer from the high-speed differential trace layers of the first layer arrangement; and
laminating the fifth layer arrangement between the second and third layer arrangements, such that at least one reference plane separates the low-speed trace layer from the patterned power layers and at least one other reference plane separates the low-speed trace layer from the high-speed differential trace layers of the third layer arrangement.
3. The method of claim 2 , wherein the fourth layer arrangement comprises at least two low-speed trace layers separated by a dielectric layer, further comprising forming a thieving pattern on each of the two low-speed trace layers, and blending the thieving patterns such that the thieving pattern on one of the two trace layers does not overlay a trace on the other trace layer.
4. The method of claim 3 , further comprising staggering the thieving patterns such that a thieving pattern feature on one of the two trace layers does not overlay a thieving pattern feature on the other trace layer.
5. The method of claim 4 , wherein each thieving pattern comprises dots laid out on a square grid, the patterns staggered such that a dot feature on one trace layer generally overlays the center of a grid square on the other trace layer.
6. The method of claim 1 , further comprising, during patterning of each patterned power layer, patterning a conductive guard ring adjacent the edges of the board and electrically direct-current isolated from the center conductive area of that power layer.
7. The method of claim 6 , further comprising electrically connecting the guard rings to each other within the circuit board.