Method and apparatus for high-speed input sampling
View Patent ↗A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
1. A method of sampling a signal, comprising:
sampling a data signal at an active transition of a clock to generate a first sampled signal;
sampling the data signal at an active transition of an inverted clock to generate a second sampled signal;
determining a next value on the output signal by determining that:
the output signal should be asserted if the first sampled signal is asserted and the second sampled signal is asserted;
determining that the output signal should be negated if the first sampled signal is negated and the second sampled signal is negated;
determining that the output signal should be toggled if the first sampled signal and the second sampled signal are in opposite logic states; and
generating the next value on the output signal responsive to the active transition of the clock.
2. The method of claim 1 , wherein the active transition of the clock is a rising edge and the active transition of the inverted clock is a falling edge.
3. The method of claim 1 , wherein the active transition of the clock is a falling edge and the active transition of the inverted clock is a rising edge.
4. The method of claim 1 , further comprising:
buffering a data input to generate the data signal; and
buffering an input clock to generate the clock and the inverted clock.
5. The method of claim 4 , further comprising delaying the data signal by a predetermined delay amount so an arrival time of the data signal at a signal sampler is substantially near an arrival time of the clock and the inverted clock at the signal sampler.
6. The method of claim 4 , wherein buffering the data input is performed by comparing the data input and a reference signal to assert the data signal if a voltage of the data input is higher than a voltage of the reference signal and negate the data signal if the voltage of the data input is lower than the voltage of the reference signal.
7. The method of claim 4 , wherein buffering the data input is performed by comparing the data input and an inverted data input to assert the data signal if a voltage of the data input is higher than a voltage of the inverted data input and negate the data signal if the voltage of the data input is lower that the voltage of the inverted data input.
8. The method of claim 1 , further comprising:
buffering a data input to generate the data signal; and
buffering an input clock and an inverted input clock to generate the clock and the inverted clock.
9. The method of claim 8 , further comprising delaying the data signal by a predetermined delay amount so an arrival time of the data signal at a signal sampler is substantially near an arrival time of the clock and the inverted clock at the signal sampler.
10. The method of claim 8 , wherein buffering the data input is performed by comparing the data input and a reference signal to assert the data signal if a voltage of the data input is higher than a voltage of the reference signal and negate the data signal if the voltage of the data input is lower than the voltage of the reference signal.
11. The method of claim 8 , wherein buffering the data input is performed by comparing the data input and an inverted data input to assert the data signal if a voltage of the data input is higher than a voltage of the inverted data input and negate the data signal if the voltage of the data input is lower than the voltage of the inverted data input.
12. The method of claim 8 , wherein buffering the input clock is performed by:
comparing the input clock and a reference signal to assert the clock if a voltage of the input clock is higher than a voltage of the reference signal and negate the clock if the voltage of the input clock is lower than the voltage on the reference signal; and
comparing the inverted input clock and the reference signal to assert the inverted clock if a voltage of the inverted input clock is higher than the voltage of the reference signal and negate the inverted clock if the voltage of the inverted input clock is lower than the voltage on the reference signal.
13. The method of claim 8 , wherein buffering the input clock is performed by comparing the input clock and the inverted input clock to assert the clock and negate the inverted clock if a voltage of the input clock is higher than a voltage of the inverted input clock, and negate the clock and assert the inverted clock if the voltage of the input clock is lower than the voltage of the inverted input clock.
14. A signal sampler, comprising:
a first sampler configured to sample a data signal at an active transition of a clock and generate a first sampled signal;
a second sampler configured to sample the data signal at an active transition of an inverted clock and generate a second sampled signal; and
an evaluator configured for generating an output signal responsive to the active transition of the clock wherein the output signal is:
asserted if the first sampled signal is asserted and the second sampled signal is asserted;
negated if the first sampled signal is negated and the second sampled signal is negated; and
a logic level opposite to a previous logic state of the output signal if the first sampled signal and the second sampled signal are in opposite logic states.
15. The signal sampler of claim 14 , wherein the active transition of the clock is a rising edge and the active transition of the inverted clock is a falling edge.
16. The signal sampler of claim 14 , wherein the active transition of the clock is a falling edge and the active transition of the inverted clock is a rising edge.
17. The signal sampler of claim 14 , wherein the first sampler is a flip-flop configured to capture the data signal at the active transition of the clock and generate the first sampled signal with a logic value sampled on the data signal.
18. The signal sampler of claim 14 , wherein the second sampler is a flip-flop configured to capture the data signal at the active transition of the inverted clock and generate the second sampled signal with a logic value sampled on the data signal.
19. The signal sampler of claim 14 , further comprising:
a first input buffer operably coupled to a data input and configured to generate the data signal; and
a second input buffer operably coupled to an input clock and an inverted input clock configured to generate the clock and the inverted clock.
20. The signal sampler of claim 19 , further comprising a matched delay operably coupled to an output of the first input buffer and configured to delay the data signal by a predetermined delay amount so an arrival time of the data signal to the signal sampler is substantially near an arrival time of the clock and the inverted clock at the signal sampler.
21. The signal sampler of claim 19 , wherein the first input buffer comprises a first differential buffer operably coupled to the data input and a reference signal, the first differential buffer configured to assert the data signal if a voltage of the data input is higher than a voltage of the reference signal and negate the data signal if the voltage of the data input is lower than the voltage of the reference signal.
22. The signal sampler of claim 19 , wherein the first input buffer comprises a first differential buffer operably coupled to the data input and an inverted data input, the first differential buffer configured to assert the data signal if a voltage of the data input is higher than a voltage of the inverted data input and negate the data signal if the voltage of the data input is lower than the voltage of the inverted data input.
23. The signal sampler of claim 14 , further comprising:
a first input buffer operably coupled to a data input and configured to generate the data signal; and
a pair of input buffers operably coupled to an input clock and an inverted input clock and configured to generate the clock and the inverted clock.
24. The signal sampler of claim 23 , further comprising a matched delay operably coupled to an output of the first input buffer and configured to delay the data signal by a predetermined delay amount so an arrival time of the data signal to the signal sampler is substantially near an arrival time of the clock and the inverted clock at the signal sampler.
25. The signal sampler of claim 23 , wherein the first input buffer comprises a first differential buffer operably coupled to the data input and a reference signal, the first differential buffer configured to assert the data signal if a voltage of the data input is higher than a voltage of the reference signal and negate the data signal if the voltage of the data input is lower than the voltage of the reference signal.
26. The signal sampler of claim 23 , wherein the first input buffer comprises a first differential buffer operably coupled to the data input and an inverted data input, the first differential buffer configured to assert the data signal if a voltage of the data input is higher than a voltage of the inverted data input and negate the data signal if the voltage of the data input is lower than the voltage of the inverted data input.
27. The signal sampler of claim 23 , wherein the pair of input buffers comprises a pair of differential clock buffers wherein:
a first differential clock buffer operably coupled to the input clock and a reference signal is configured to assert the clock if a voltage of the input clock is higher than a voltage of the reference signal and negate the clock if the voltage of the input clock is lower than the voltage of the reference signal; and
a second differential clock buffer operably coupled to the inverted input clock and the reference signal is configured to assert the inverted clock if a voltage of the inverted input clock is higher than the voltage of the reference signal and negate the inverted clock if the voltage of the inverted input clock is lower than the voltage of the reference signal.
28. The signal sampler of claim 23 , wherein the pair of input buffers comprises a pair of differential clock buffers wherein:
a first differential clock buffer operably coupled to the input clock and the inverted input clock is configured to assert the clock if a voltage of the input clock is higher than a voltage of the inverted input clock and negate the clock if the voltage of the input clock is lower than the voltage of the inverted input clock; and
a second differential clock buffer operably coupled to the inverted input clock and the input clock is configured to assert the inverted clock if the voltage of the inverted input clock is higher than the voltage of the input clock and negate the inverted clock if the voltage of the inverted input clock is lower than the voltage of the input clock.
29. A semiconductor device including at least one signal sampler, the at least one signal sampler comprising:
a first sampler configured to sample a data signal at an active transition of a clock and generate a first sampled signal;
a second sampler configured to sample the data signal at an active transition of an inverted clock and generate a second sampled signal; and
an evaluator configured for generating an output signal responsive to the active transition of the clock wherein the output signal is:
asserted if the first sampled signal is asserted and the second sampled signal is asserted;
negated if the first sampled signal is negated and the second sampled signal is negated; and
a logic level opposite to a previous logic state of the output signal if the first sampled signal and the second sampled signal are in opposite logic states.
30. A semiconductor wafer, comprising:
at least one semiconductor device including at least one signal sampler, the at least one signal sampler comprising:
a first sampler configured to sample a data signal at an active transition of a clock and generate a first sampled signal;
a second sampler configured to sample the data signal at an active transition of an inverted clock and generate a second sampled signal; and
an evaluator configured for generating an output signal responsive to the active transition of the clock wherein the output signal is:
asserted if the first sampled signal is asserted and the second sampled signal is asserted;
negated if the first sampled signal is negated and the second sampled signal is negated; and
a logic level opposite to a previous logic state of the output signal if the first sampled signal and the second sampled signal are in opposite logic states.
31. An electronic system, comprising:
at least one input device;
at least one output device;
at least one processor; and
at least one memory device comprising, at least one semiconductor memory including at least one signal sampler, the at least one signal sampler comprising:
a first sampler configured to sample a data signal at an active transition of a clock and generate a first sampled signal;
a second sampler configured to sample the data signal at an active transition of an inverted clock and generate a second sampled signal; and
an evaluator configured for generating an output signal responsive to the active transition of the clock wherein the output signal is:
asserted if the first sampled signal is asserted and the second sampled signal is asserted;
negated if the first sampled signal is negated and the second sampled signal is negated; and
a logic level opposite to a previous logic state of the output signal if the first sampled signal and the second sampled signal are in opposite logic states.