Semiconductor device

1. A semiconductor device, comprising:

a semiconductor chip;

first and second metal layers formed on a first main surface of said semiconductor chip;

a first conductive layer layered on a second main surface of said semiconductor chip, consisting of a plurality of conductive films;

a second conductive layer layered on said first metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in said first conductive layer as viewed from said semiconductor chip; and

a third conductive layer layered on said second metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in said first conductive layer as viewed from said semiconductor chip,

wherein said plurality of conductive films comprise

a nickel film; and

a low contact resistance conductive film having contact resistance with said semiconductor chip which is lower than that of said nickel film,

and wherein said low contact resistance conductive film and said nickel film are formed in this order from said semiconductor chip.

2. The semiconductor device according to claim 1 , further comprising

first to third electrode plates provided on said first to third conductive layers with solders interposed therebetween, respectively.

3. The semiconductor device according to claim 1 , wherein

said semiconductor chip comprises an N-type impurity region formed in said second main surface, and

said low contact resistance conductive film is a titanium film.

4. The semiconductor device according to claim 2 , wherein

said semiconductor chip comprises an N-type impurity region formed in said second main surface, and

said low contact resistance conductive film is a titanium film.

5. The semiconductor device according to claim 1 , wherein

said semiconductor chip comprises a P-type impurity region formed in said second main surface, and

said low contact resistance conductive film consists of an aluminum film and a molybdenum film which are layered in this order from said semiconductor chip.

6. The semiconductor device according to claim 2 , wherein

said semiconductor chip comprises a P-type impurity region formed in said second main surface, and

said low contact resistance conductive film consists of an aluminum film and a molybdenum film which are layered in this order from said semiconductor chip.

7. The semiconductor device according to claim 1 , wherein

said first and second metal layers each include the same metal element as portions of said low contact resistance conductive films being contact with said first and second metal layers, respectively.

8. The semiconductor device according to claim 2 , wherein

said first and second metal layers each include the same metal element as portions of said low contact resistance conductive films being contact with said first and second metal layers, respectively.

9. The semiconductor device according to claim 1 , wherein

said semiconductor chip is an insulated gate transistor.

10. The semiconductor device according to claim 2 , wherein

said semiconductor chip is an insulated gate transistor.

11. The semiconductor device according to claim 3 , wherein

said semiconductor chip is an insulated gate transistor.

12. The semiconductor device according to claim 4 , wherein

said semiconductor chip is an insulated gate transistor.

13. The semiconductor device according to claim 5 , wherein

said semiconductor chip is an insulated gate transistor.

14. The semiconductor device according to claim 6 , wherein

said semiconductor chip is an insulated gate transistor.

15. The semiconductor device according to claim 7 , wherein

said semiconductor chip is an insulated gate transistor.

16. The semiconductor device according to claim 8 , wherein

said semiconductor chip is an insulated gate transistor.