IP Library Granted Patent US 7,075,766
Granted Patent B2
US 7,075,766 · App. 10/918,499 · Granted Jul 11, 2006

Fault detection in a LED bias circuit

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Quick Facts
Patent No.
US 7,075,766
App. No.
10/918,499
Granted
Jul 11, 2006
Kind
B2
Abstract

The present invention detects single faults that would cause the current flowing through the light source to increase by a significant amount over the intended value. When the fault is a small leakage path to Ground potential from the light source cathode, it can be detected while maintaining operation of the light source within eye safety limits. In addition, the fault may be detected without activating the light source.

Claims (64)

1. A circuit comprising:

a first switch, connected to power, having an input;

a light source connected to the first switch;

a current source, connected to power;

a second switch connected to the current source and the light source, having an input;

two bias current legs, electrically connected in parallel, interposing the light source and ground;

a first comparator, having a first input connected to the light source and a second input that receives a reference voltage signal;

a second comparator, having a first input connected to one of the bias current legs and a second input connected to another of the bias current legs; and

a drive circuit, having outputs connected to the input of the first switch, the input of the second switch, and the bias current legs, receiving an output from the first and second comparators.

2. The circuit, as in claim 1 , each bias current leg including:

a current-sensing resistor connected to the light source; and

a current magnifying circuit, connected to the current-sensing resistor.

3. The circuit as in claim 1 , further comprising:

a bias resistor interposing the bias current legs and ground;

an amplifier, having a first input receiving a voltage reference signal, a second input connected to the bias resistor, and an output connected to the bias legs; and

a third comparator, having a first input receiving a high voltage signal, having a second input connected to the bias resistor; and

the drive circuit further receiving the output from the third comparator.

4. The circuit, as in claim 3 , further comprising:

a fourth comparator, having a first input connected to the bias resistor and a second input receiving a low voltage signal; and

the drive circuit, further receiving the output from the fourth comparator.

5. The circuit, as in claim 3 , each bias current leg including:

a current-sensing resistor connected to the light emitting diode;

a current magnifying circuit, connected to the current-sensing resistor; and

a transistor, providing an output to the current magnifying circuit, an input connected to the amplifier output, and an input connected to the bias resistor.

6. The circuit, as in claim 5 , wherein the transistor is a field effect transistor.

7. The circuit, as in claim 6 , wherein the field effect transistors for the two bias current legs have the same size.

8. The circuit, as in claim 1 , further comprising a substrate that includes the switches, the bias current legs, the first and second comparators, and the drive circuit.

9. The circuit, as in claim 8 , each bias current leg including:

a current-sensing resistor connected to the light source; and

a current magnifying circuit, connected to the current-sensing resistor.

10. The circuit, as in claim 8 , further comprising:

a bias resistor interposing the bias current legs and ground;

an amplifier, having a first input receiving a voltage reference signal, a second input connected to the bias resistor, and an output connected to both bias legs;

a third comparator, having a first input receiving a high voltage signal, having a second input connected to the bias resistor;

the drive circuit, further receiving the output from the third comparator; and

wherein the substrate includes the amplifier and the third comparator.

11. The circuit, as in claim 10 , further comprising a fourth comparator, positioned on the substrate, having a first input connected to the bias resistor and a second input receiving a low voltage signal.

12. The circuit, as in claim 10 , each bias current leg including:

a current-sensing resistor connected to the light source;

a current magnifying circuit, connected to the current sensing resistor; and

a transistor, providing an output to the current magnifying circuit, an input connected to the amplifier output, and an input connected to the bias resistor.

13. The circuit, as in claim 12 , wherein the transistor is a field effect transistor.

14. The circuit, as in claim 13 , wherein the field effect transistors for the two bias current legs have the same size.

15. The circuit, as in claim 1 , wherein the first comparator and the second comparator are adapted to determine a fault when the light source is turned off.

16. A circuit comprising:

a first switch connected to power, having an input,

a light source adapted to receive power from the first switch;

a current source, connected to power;

a second switch connected to the current source and the light source, having an input;

two bias current legs, electrically connected in parallel, interposing the light source and ground;

a first comparator, having a first input connected to the light source and a second input that receives a reference voltage signal;

a second comparator, having a first input connected to one of the bias current legs and a second input connected to another of the bias current legs; and

a drive circuit, having outputs connected to the input of the first switch, the input of the second switch, and the bias current legs, receiving an output from the first and second comparators;

wherein the output of the first comparator and the second comparator are generated in response to a fault condition in the circuit; and

wherein the first switch and the second switch are turned on in response to output of the drive circuit.

17. The circuit as in claim 16 , wherein the first comparator and the second comparator are adapted to determine a fault when the light source is turned off.

18. A method of fault detection in a circuit, the method comprising:

passing a voltage signal across a first switch connected to a light source;

passing a current signal across a second switch connected to a first bias current leg and a second bias current leg;

comparing an output voltage at the first bias current leg and an output voltage at the second bias current leg using a first comparator;

comparing an output voltage at the light source and a reference voltage using a second comparator; and

turning off the first switch and the second switch in response to determining the fault.

19. The method of claim 18 , wherein determining the fault based on the output of the first comparator and the second comparator is performed when the light source is turned on.

20. The method of claim 18 , wherein determining the fault based on the output of the first comparator and the second comparator is performed when the light source is turned off.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2011
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: WISTRON CORPORATION
Reel/Frame 027096/0255 →
RELEASE OF SECURITY INTEREST AT 017207/0882 Recorded Oct 14, 2011
From: CITICORP NORTH AMERICA, INC.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD., SUCCESSOR IN INTEREST TO AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 027068/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0518 →
SECURITY AGREEMENT Recorded Feb 24, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: CITICORP NORTH AMERICA, INC.
Reel/Frame 017207/0882 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2005
From: MOYER, VINCENT C.; BRONSON, MICHAEL JOHN
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 015623/0027 →