Radio frequency CMOS amplifier with enhanced linearity and power efficiency
View Patent ↗In general, the disclosure is directed to techniques for enhancing power efficiency and linearity in an RF power amplifier. In accordance with the invention, a combination of different class power amplifiers is implemented in a parallel configuration to overcome the trade-off that exists between power efficiency and linearity. In particular, a class A amplifier and a class B amplifier are arranged in parallel to produce a combined amplifier output for an input signal. With bias voltages set to achieve a desired operating ratio between the class A and class B amplifier, the combined amplifier can provide a high power gain over a larger input range. In addition, the class B amplifier can provide increased power efficiency for larger inputs.
1. A radio frequency (RF) amplifier circuit comprising:
a class A power amplifier;
a class B power amplifier coupled to the class A power amplifier such that the class A and class B RF power amplifiers produce a combined amplifier output for an RF input signal; and
a tank circuit coupled to the class A and class B power amplifiers.
2. The amplifier circuit of claim 1 , wherein the class A and class B power amplifiers are coupled in parallel to form an input transconductor cell.
3. The amplifier circuit of claim 1 , wherein the class A power amplifier is biased to operate in a saturation region and the class B power amplifier is biased to amplify approximately half of every cycle of the input signal.
4. The amplifier circuit of claim 1 , wherein the class A power amplifier compensates gain depression of the class B power amplifier at low power inputs.
5. The amplifier circuit of claim 1 , wherein a size of a first transistor associated with the class A power amplifier is substantially smaller than a size of a second transistor associated with the class B power amplifier.
6. The amplifier circuit of claim 1 , wherein the class A power amplifier includes a first transistor and the class B power amplifier includes a second transistor, the first and second transistors being coupled via a common drain node.
7. The amplifier circuit of claim 6 , wherein the first and second transistors comprise MOSFETS.
8. The amplifier circuit of claim 6 , wherein the class A power amplifier is a first class A power amplifier, the circuit further comprising a second class A power amplifier having a source coupled to the common drain node of the first class A power amplifier and the class B power amplifier, wherein the tank circuit is coupled to the first class A power amplifier and the class B power amplifier via the second class A power amplifier.
9. The amplifier circuit of claim 8 , wherein the tank circuit includes an inductor and capacitor coupled in parallel to a drain of the second class A power amplifier.
10. The amplifier circuit of claim 1 , wherein the class A power amplifier is biased such that a bias voltage of the class A power amplifier is greater than a threshold voltage of the class A power amplifier.
11. The amplifier circuit of claim 1 , wherein the class B power amplifier is biased at approximately a threshold voltage of the class B power amplifier.
12. The amplifier circuit of claim 1 , wherein the class A and class B amplifiers comprise CMOS amplifiers.
13. A method comprising amplifying an input radio frequency (RF) signal with combined outputs of a class A power amplifier and a class B power amplifier and applying the combined outputs to a tank circuit coupled to the class A and class B power amplifiers.
14. The method of claim 13 , further comprising:
biasing the class A power amplifier to operate in a saturation region; and
biasing the class B power amplifier to amplify approximately half of every cycle of the input signal.
15. The method of claim 14 , wherein biasing the class A power amplifier to operate in a saturation region comprises biasing the class A power amplifier with a bias voltage that is greater than a threshold voltage of the class A amplifier.
16. The method of claim 14 , wherein biasing the class B power amplifier to amplify approximately half of every cycle of the input signal comprises biasing the class B power amplifier with a bias voltage that is at approximately a threshold voltage of the class B power amplifier.
17. The method of claim 13 , wherein the class A power amplifier is a first class A power amplifier, and further comprising amplifying the combined outputs of the first class A power amplifier and the class B power amplifier with a second class A power amplifier.
18. The method of claim 17 , wherein the second class A power amplifier is connected to a common drain node of the parallel coupled first class A and class B power amplifiers.
19. The method of claim 17 , wherein the tank circuit includes an inductor and a capacitor coupled in parallel, the method further comprising a filtering the output of the second class A amplifier with the tank circuit.
20. A wireless device comprising:
a medium access control (MAC) unit that interacts with a host device to coordinate access to a radio frequency (RF) channel for an input signal generated by the host device;
an RF transmit power amplifier circuit to amplify the input signal, the RF transmit power amplifier circuit comprising a class A power amplifier and a class B power amplifier coupled to the class A power amplifier such that the class A and class B power amplifiers produce a RF combined amplifier output signal for the input signal a tank circuit coupled to the class A and class B power amplifiers; and
a transmit antenna to transmit the RF amplifier output signal to a wireless network.
21. The wireless device of claim 20 , wherein the class A and class B power amplifiers are coupled in parallel to form an input transconductor cell.
22. The wireless device of claim 20 , wherein the class A power amplifier is biased to operate in a saturation region and the class B power amplifier is biased to amplify approximately half of every cycle of the input signal.
23. The wireless device of claim 20 , wherein the class A power amplifier compensates gain depression of the class B power amplifier at low power inputs.
24. The wireless device of claim 20 , wherein a size of a first transistor associated with the class A power amplifier is substantially smaller than a size of a second transistor associated with the class B power amplifier.
25. The wireless device of claim 20 , wherein the class A power amplifier includes a first transistor and the class B power amplifier includes a second transistor, the first and second transistors being coupled via a common drain node.
26. The wireless device of claim 25 , wherein the first and second transistors comprise MOSFETS.
27. The wireless device of claim 25 , wherein the class A power amplifier is a first class A power amplifier, the circuit further comprising a second class A power amplifier having a source coupled to the common drain node of the first class A power amplifier and the class B power amplifier.
28. The wireless device of claim 27 , further comprising a tank circuit including an inductor and capacitor coupled in parallel to a drain of the second class A power amplifier.
29. The wireless device of claim 20 , wherein the class A power amplifier is biased such that a bias voltage of the class A power amplifier is greater than a threshold voltage of the class A power amplifier.
30. The wireless device of claim 20 , wherein the class B power amplifier is biased at approximately a threshold voltage of the class B power amplifier.
31. The wireless device of claim 20 , further comprising:
a receiver to receive a wireless signal from a wireless network; and
a receive power amplifier circuit to amplify a received signal, the receive power amplifier circuit comprising a class A power amplifier and a class B power amplifier coupled to the class A power amplifier such that the class A and class B power amplifiers produce a combined amplifier output for an input signal.
32. The wireless device of claim 31 , wherein the class A power amplifier includes a first transistor and the class B power amplifier includes a second transistor, the first and second transistors being coupled via a common drain node.
33. The wireless device of claim 32 , wherein the class A power amplifier of the receive power amplifier circuit is a first class A power amplifier, the circuit further comprising a second class A power amplifier having a source coupled to the common drain node of the first class A power amplifier and the class B power amplifier.
34. The wireless device of claim 33 , wherein the a tank circuit includes an inductor and capacitor coupled in parallel to a drain of the second class A power amplifier.