Signal-processing apparatus and electronic apparatus using same

1 . A signal-processing apparatus comprising: an instruction-parallel processor; a data-parallel processor; and a plurality of pieces of dedicated hardware,

wherein said instruction-parallel processor performs audio compression/decompression and non-routine or less-heavy operation of image compression/decompression,

wherein said data-parallel processor performs, of the image compression/decompression, routine or heavy operation, and

wherein said plurality of pieces of dedicated hardware perform, of the image compression/decompression, comparatively heavy processing.

2 . A signal-processing apparatus according to claim 1 , further comprising:

a first instruction bus;

a first data bus;

a first shared memory; and

an input and output interface,

wherein each of said instruction-parallel processor, said data-parallel processor, said plurality of pieces of dedicated hardware and said input and output interface comprises a local memory, said instruction-parallel processor, said data-parallel processor and said plurality of pieces of dedicated hardware are connected to said first instruction bus,

wherein an instruction for said instruction-parallel processor to control said data-parallel processor and said plurality of hardware is communicated through said first instruction bus, and

wherein said local memory of said instruction-parallel data processor, said local memory of said data-parallel processor, said local memories of said plurality of pieces of dedicated hardware, said first shared memory and said local memory of said input and output interface are connected to said first data bus, and data transfer is performed among these memories.

3 . A signal-processing apparatus according to claim 2 , further comprising:

a second data bus;

a second shared memory; and

a bridge unit connecting said first data bus and said second data bus,

wherein said local memory of said data-parallel processor, said local memories of said plurality of pieces of dedicated hardware, said first shared memory and said local memory of said input and output interface are connected to said first data bus, and data transfer is performed among these memories,

wherein said local memory of said instruction-parallel processor and said second shared memory are connected to said second data bus, and data transfer is performed between these memories, and

wherein data transfer between said memories connected to said first data bus and said memories connected to said second data bus is performed through said bridge unit.

4 . A signal-processing apparatus according to claim 3 , further comprising a control processor,

wherein said instruction-parallel processor controls said data-parallel processor and said plurality of pieces of dedicated hardware through said control processor.

5 . A signal-processing apparatus according to claim 4 , further comprising a second instruction bus,

wherein said instruction-parallel processor, said control processor and a part of said plurality of pieces of dedicated hardware are connected to said first instruction bus,

wherein said control processor, said data-parallel processor and the remainder of said plurality of pieces of dedicated hardware, the remainder being not connected to said first instruction bus, are connected to said second instruction bus, and

wherein said instruction-parallel processor controls the part of said plurality of pieces of dedicated hardware, and controls, through said control processor, said data-parallel processor and the remainder of said plurality of pieces of hardware.

6 . A signal-processing apparatus according to claim 1 , wherein said data-parallel processor comprises a plurality of processing units, and

wherein a number of said plurality of processing units of said data-parallel processor is determined according to a compressed or decompressed image size.

7 . A signal-processing apparatus according to claim 1 , wherein said data-parallel processor comprises a plurality of processing units, and

wherein a number of said plurality of processing units of said data-parallel processor is determined according to at least one of a power supply voltage and an operating frequency.

8 . A signal-processing apparatus according to claim 1 , wherein processing performed by said plurality of pieces of dedicated hardware includes at least one of variable-length coding processing, variable-length decoding processing, video input and output processing, motion detection processing, motion compensation processing, DCT (discrete cosine transform) processing, inverse DCT processing, quantization processing, inverse quantization processing and de-blocking filtering processing.

9 . A signal-processing apparatus according to claim 5 , wherein processing performed by the part, of said plurality of pieces of dedicated hardware, the part being connected to said first instruction bus, is variable-length coding processing and/or variable-length decoding processing.

10 . An electronic apparatus comprising a signal-processing apparatus, said signal-processing apparatus comprising: an instruction-parallel processor; a data-parallel processor; and a plurality of pieces of dedicated hardware,

wherein said instruction-parallel processor performs audio compression/decompression and non-routine or less-heavy operation of image compression/decompression,

wherein said data-parallel processor performs, of the image compression/decompression, routine or heavy operation,

wherein said plurality of pieces of dedicated hardware perform, of the image compression/decompression, comparatively heavy processing, and

wherein said signal-processing apparatus performs at least one of audio compression processing, audio decompression processing, image compression processing and image decompression processing.

11 . An electronic apparatus according to claim 10 , further comprising: a reproducer; a demodulator/error corrector; a memory; and a plurality of D/A converters,

wherein said reproducer reproduces modulated coded signals from a recording medium loaded therein,

wherein said demodulator/error corrector demodulates the modulated coded signals reproduced by said reproducer, error-corrects the demodulated signals, and outputs the error-corrected signals as coded data,

wherein said signal-processing apparatus decodes the coded data outputted by said demodulator/error corrector, and outputs the decoded data as video data and audio data,

wherein said memory stores data before decoding, during decoding and after decoding, and

wherein said plurality of D/A converters D/A-convert the video data and the audio data outputted by said signal-processing apparatus, and outputs an analog video output and an analog audio output.

12 . An electronic apparatus according to claim 10 , further comprising: a plurality of A/D converters; a memory; an error corrector/modulator; and a recorder,

wherein said plurality of A/D converters A/D convert an inputted analog video input and analog audio input, and outputs video data and audio data,

wherein said signal-processing apparatus encodes the video data and the audio data outputted by said plurality of A/D converters, and outputs coded data,

wherein said memory stores data before encoding, during encoding and after encoding,

wherein said error corrector/modulator adds an error correcting code to the coded data encoded by said signal-processing apparatus, modulates the coded data, and outputs the modulated data as coded signals, and

wherein said recorder records the coded signals outputted by said error corrector/modulator onto a recording medium loaded therein.

13 . An electronic apparatus comprising the electronic apparatus according to claim 11 and the electronic apparatus according to claim 12 .

14 . An electronic apparatus according to claim 11 , wherein the recording medium is an optical disk.

15 . An electronic apparatus according to claim 11 , wherein the recording medium is a magnetic disk.

16 . An electronic apparatus according to claim 11 , wherein the recording medium is a semiconductor memory.