High voltage and low on-resistance LDMOS transistor having radiation structure and isolation effect
View Patent ↗A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.
1. A transistor, comprising:
a P-substrate;
a first diffusion region and a second diffusion region, having N conductivity-type ions form an N-well in said P-substrate, wherein said first diffusion region comprises an extended drain region;
a drain diffusion region, containing N+ conductivity-type ions, forming a drain region in said extended drain region;
a plurality of P-field blocks, formed in said extended drain region encircling said drain region, wherein sizes and shapes of said P-field blocks can be adjusted for adjusting junction fields;
a source diffusion region, having N+ conductivity-type ions, wherein said source diffusion region forms a source region in said N-well which is formed by said second diffusion region and encircles said drain region;
a channel, formed between said drain region and said source region;
a gate electrode, formed over said channel to control a current flow in said channel;
a contact diffusion region, containing P+ conductivity-type ions, wherein said contact diffusion region forms a contact region in said N-well which is formed by said second diffusion region; and
an isolation P-well, formed in said N-well which is formed by said second diffusion region for preventing from breakdown, wherein said isolation P-well formed in said second diffusion region encloses said source region and said contact region.
2. The transistor as claimed in claim 1 , wherein said source diffusion region and said P-field blocks encircle said drain region to achieve isolation effect.
3. The transistor as claimed in claim 2 , wherein said P-field blocks are formed in said extended drain region of said N-well, wherein said N-well depletes a drift region, equalizes the capacitance of parasitic capacitors between said drain region and said source region, and decreases an on-resistance of said channel.
4. The transistor as claimed in claim 2 , wherein said P-field blocks can be designed in different patterns, sizes and shapes to increase the breakdown voltage and decrease the on-resistance.
5. The transistor as claimed in claim 4 , wherein said P-field blocks are in ringlike shape, wherein modulating an internal diameter and an external diameter of said P-field blocks can increase the breakdown voltage and decrease the on-resistance.
6. The transistor as claimed in claim 2 , wherein said source diffusion region can be in ringlike shape and at least one P-field block is located in a single radial direction, wherein modulating the quantities and shapes of said P-field blocks can increase the breakdown voltage and decrease the on-resistance.
7. The transistor as claimed in claim 2 , wherein said source diffusion region can be in polygonal shape, wherein adjusting a length of side and interior angle said source diffusion region in polygonal shape facilitates the combination with other transistors, which forms a common source structure for die-space saving.
8. A transistor, comprising:
a P-substrate;
an N-well, formed in said P-substrate, having an extended drain region;
a drain region, containing N+ conductivity-type ions, formed in said extended drain region;
a plurality of P-field blocks, formed in said extended drain region encircling said drain region, wherein sizes and shapes of said P-field blocks can be adjusted for adjusting junction fields;
a source region, having N+ conductivity-type ions, formed in said N-well and encircling said drain region;
a channel, formed between said drain region and said source region;
a gate electrode, formed over said channel to control a current flow in said channel;
a contact region, containing P+ conductivity-type ions, formed in said N-well; and
an isolation P-well, formed in said N-well, for preventing from breakdown, wherein said isolation P-well encloses said source region and said contact region.
9. The transistor as claimed in claim 8 , wherein said source region and said P-field blocks encircle said drain region to achieve isolation effect.
10. The transistor as claimed in claim 9 , wherein said P-field blocks are formed in said extended drain region of said N-well, wherein said N-well depletes a drift region equalizes the capacitance of parasitic capacitors between said drain region and said source region, and decreases an on-resistance of said channel.
11. The transistor as claimed in claim 9 , wherein said P-field blocks can be designed in different patterns, sizes and shapes to increase the breakdown voltage and decrease the on-resistance.
12. The transistor as claimed in claim 9 , wherein said P-field blocks are in ringlike shape wherein modulating an internal diameter and an external diameter of said P-field blocks can increase the breakdown voltage and decrease the on-resistance.
13. The transistor as claimed in claim 9 , wherein said source region can be in ringlike shape and at least one P-field block is located in a single radial direction, wherein modulating the quantities and shapes of said P-field blocks can increase the breakdown voltage and decrease the on-resistance.
14. The transistor as claimed in claim 9 , wherein said source region can be in polygonal shape, wherein adjusting a length of side and interior angle of said source region in polygon shape facilitates the combination with other transistors, which forms a common source structure for die-space saving.