NAND memory arrays and methods

1. A method of forming a NAND memory array, comprising:

forming a first dielectric layer on a first portion of a semiconductor substrate;

forming a second dielectric layer on a second portion of the semiconductor substrate that is adjacent to the first portion of the semiconductor substrate so that the first and second dielectric layers are adjacent to each other, wherein the first dielectric layer is thicker than the second dielectric layer and wherein the second dielectric layer is formed independently of the first dielectric layer;

forming a first gate stack on the first dielectric layer to form a drain select gate;

forming a string of second gate stacks on the second dielectric layer to form a NAND string of floating-gate memory cells, wherein a first memory cell of the NAND string is adjacent the drain select gate; and

forming a third gate stack on the second dielectric layer to form a source select gate adjacent a last memory cell of the NAND string.

2. The method of claim 1 , wherein the source and drain select gates and the NAND string form a column of the memory array.

3. The method of claim 1 , wherein the drain select gate and the first memory cell of the NAND string share a first source/drain region formed in the substrate and the source select gate and the last memory cell of the NAND string share a second source/drain region formed in the substrate.

4. The method of claim 1 , wherein the drain select gate further comprises a drain select line formed on the first dielectric layer, the source select gate further comprises a source select line formed on the second dielectric layer, and each of the memory cells further comprises a floating gate formed on the second dielectric layer, an intergate dielectric layer formed on the floating gate, and a word line formed on the intergate dielectric layer.

5. The method of claim 1 , wherein each of the memory cells and the source select gate further comprise a first conductive layer formed on the second dielectric layer, a third dielectric layer formed on the first conductive layer, and a second conductive layer formed on the third dielectric layer, and wherein the drain select gate comprises the first conductive layer formed on the first dielectric layer, the third dielectric layer formed on the first conductive layer, and the second conductive layer formed on the third dielectric layer.

6. The method of claim 5 , wherein the first conductive layer is a polysilicon layer.

7. The method of claim 6 , wherein the polysilicon layer is conductively doped.

8. The method of claim 6 , wherein the second conductive layer is selected from the group consisting of a polysilicon layer, a metal layer, a metal-containing layer, a layer containing one or more conductive materials, and one or more conductive layers.

9. The method of claim 8 , wherein the third dielectric layer comprises one or more layers of dielectric material.

10. The method of claim 8 , wherein each of the first and second dielectric layers are oxide layers.

11. A method of forming a NAND memory array, comprising:

forming a first dielectric layer on a first portion of a semiconductor substrate;

forming a second dielectric layer on a second portion of the semiconductor substrate that is adjacent to the first portion of the semiconductor substrate so that the first and second dielectric layers are adjacent to each other, wherein the first dielectric layer is thicker than the second dielectric layer and wherein the second dielectric layer is formed independently of the first dielectric layer;

nitridizing the second dielectric layer;

forming a first gate stack on the first dielectric layer to form a drain select gate; and

forming a string of second gate stacks on the nitridized second dielectric layer to form a NAND string of floating-gate memory cells, wherein a first memory cell of the NAND string is adjacent the drain select gate.

12. The method of claim 11 further comprises protecting the first dielectric layer from the nitridation.

13. A method of forming a NAND memory array, comprising:

forming a plurality of first gate stacks on a first dielectric layer formed on a substrate, wherein the first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array;

forming a second gate stack on a second dielectric layer formed on the substrate adjacent the first dielectric layer, wherein the second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent a first end of the NAND string, and wherein the second dielectric layer is thicker than the first dielectric layer; and

forming a third gate stack on the first dielectric layer adjacent a second end of the NAND string, wherein the first dielectric layer with the third gate stack formed thereon forms a source select gate adjacent the second end of the NAND string.

14. The method of claim 13 , wherein the second gate stack comprises a drain select line formed on the second dielectric layer.

15. The method of claim 13 , wherein the each of the first gate stacks comprises a floating gate formed on the first dielectric layer, an intergate dielectric layer formed on the floating gate, and a word line formed on the intergate dielectric layer.

16. The method of claim 13 , wherein each of the first gate stacks comprises a first conductive layer formed on the first dielectric layer, a third dielectric layer formed on the first conductive layer, and a second conductive layer formed on the third dielectric layer, and wherein the second gate stack comprises the first conductive layer formed on the second dielectric layer, the third dielectric layer formed on the first conductive layer, and the second conductive layer formed on the third dielectric layer.

17. The method of claim 13 , wherein the third gate stack comprises a source select line formed on the first dielectric layer.

18. The method of claim 13 , wherein the source and drain select gates are field effect transistors and each of the memory cells is a floating-gate memory cell.

19. The method of claim 18 , wherein each of the floating-gate memory cells is a floating-gate transistor.

20. The method of claim 13 , wherein the source and drain select gates and the NAND string form a column of the memory array.

21. The method of claim 13 , wherein the drain select gate and an adjacent memory cell of the NAND string share a source/drain region formed in the substrate.

22. A method of forming a NAND memory array, comprising:

forming a plurality of first gate stacks on a first dielectric layer formed on a substrate, wherein the first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array; and

forming a second gate stack on a second dielectric layer formed on the substrate adjacent the first dielectric layer, wherein the second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent a first end of the NAND string, and wherein the second dielectric layer is thicker than the first dielectric layer;

wherein the first dielectric layer is nitridized before forming the first gate stacks thereon.

23. A method of forming a NAND memory array, comprising:

forming a first dielectric layer on a semiconductor substrate;

forming a hard mask layer on the first dielectric layer;

removing a portion of the hard mask layer and the first dielectric layer to expose a portion of the substrate adjacent a remaining portion of the first dielectric layer;

forming a second dielectric layer on the exposed portion of the substrate, wherein the second dielectric layer is thinner than the first dielectric layer;

removing the hard mask layer from the remaining portion of the first dielectric layer;

forming a first gate stack on the first dielectric layer to form a drain select gate; and

forming a string of second gate stacks on the second dielectric layer to form a NAND string of floating-gate memory cells, wherein a first memory cell of the NAND string is adjacent the drain select gate.

24. The method of claim 23 further comprises nitridizing the second dielectric layer before forming the second gate stacks thereon.

25. The method of claim 23 further comprises forming a third gate stack on the second dielectric layer to form a source select gate adjacent a last memory cell of the NAND string.

26. The method of claim 23 , wherein forming a first dielectric layer on a semiconductor substrate comprises thermally growing the first dielectric layer on the semiconductor substrate.

27. The method of claim 23 , wherein forming a second dielectric layer on the exposed portion of the substrate comprises thermally growing the second dielectric layer on the exposed portion of the substrate.

28. The method of claim 23 , wherein removing a portion of the hard mask layer and the first dielectric layer to expose a portion of the substrate comprises patterning the hard mask layer and selectively etching through the hard mask layer and the first dielectric layer so as to stop at the substrate.

29. The method of claim 23 , wherein first and second dielectric layers are thermal oxide layers.

30. The method of claim 23 , wherein the hard mask layer is a nitride layer.

31. A method of forming a NAND memory array, comprising:

forming a first dielectric layer on a semiconductor substrate;

forming a hard mask layer on the first dielectric layer;

patterning the hard mask layer for removing a portion of the hard mask layer and the first dielectric layer to expose a portion of the substrate adjacent a remaining portion of the first dielectric layer;

removing the portion of the hard mask layer and the first dielectric layer to expose the portion of the substrate;

forming a second dielectric layer on the exposed portion of the substrate, wherein the second dielectric layer is thinner than the first dielectric layer;

removing the hard mask layer from the remaining portion of the first dielectric layer;

forming a first conductive layer on the first and second dielectric layers;

forming a third dielectric layer of the first conductive layer;

forming a second conductive layer on the third dielectric layer;

removing portions of the second conductive layer, the third dielectric layer, and the first conductive layer to expose portions of the first and second dielectric layers and to form a first gate stack on the first dielectric layer, a second gate stack on the second dielectric layer, and a string of third gate stacks on the second dielectric layer between the first and second gate stacks;

wherein the first dielectric layer with the first gate stack formed thereon forms a drain select gate, the second dielectric layer with the second gate stack formed thereon forms a source select gate, and the second dielectric layer with the string of third gate stacks formed thereon forms a NAND string of memory cells between the drain and source select gates.

32. The method of claim 31 further comprises nitridizing the second dielectric layer before removing the hard mask layer.

33. The method of claim 31 , wherein forming a first dielectric layer on a semiconductor substrate comprises thermally growing an oxide on the semiconductor substrate.

34. The method of claim 31 , wherein forming a second dielectric layer on the exposed portion of the substrate comprises thermally growing an oxide layer on the exposed portion of the substrate.

35. The method of claim 31 , wherein the hard mask layer is a nitride layer.

36. The method of claim 31 , wherein the first conductive layer is a polysilicon layer.

37. The method of claim 31 , wherein the second conductive layer is selected from the group consisting of a polysilicon layer, a metal layer, a metal-containing layer, a layer containing one or more conductive materials, and one or more conductive layers.

38. The method of claim 31 , wherein the third dielectric layer comprises one or more layers of dielectric material.

39. The method of claim 31 , wherein successive memory cells share a first source/drain region formed in the substrate, wherein the drain select gate and a first memory cell of the NAND string share a second source/drain region formed in the substrate, and wherein the source select gate and a last memory cell of the NAND string share a third source/drain region formed in the substrate.

40. A method of forming a NAND memory array, comprising:

forming a first oxide layer on a semiconductor substrate;

forming a nitride layer on the first oxide layer;

patterning the nitride layer for removing a portion of the nitride layer and the first oxide layer to expose a portion of the substrate adjacent a remaining portion of the first oxide layer;

removing the portion of the nitride layer and the first oxide layer to expose the portion of the substrate;

forming a second oxide layer on the exposed portion of the substrate, wherein the second oxide layer is thinner than the first oxide layer;

nitridizing the second oxide layer;

removing the nitride layer from the remaining portion of the first oxide layer;

forming a polysilicon layer on the first and second oxide layers;

forming a dielectric layer of the polysilicon layer;

forming a conductive layer on the dielectric layer;

removing portions of the conductive layer, the dielectric layer, and the polysilicon layer to expose portions of the first and second oxide layers and to form a first gate stack on the first oxide layer, a second gate stack on the second oxide layer, and a string of third gate stacks on the second oxide layer between the first and second gate stacks;

wherein the first oxide layer with the first gate stack formed thereon forms a drain select gate, the second oxide layer with the second gate stack formed thereon forms a source select gate, and the second oxide layer with the string of third gate stacks formed thereon forms a NAND string of memory cells between the drain and source select gates.

41. The method of claim 40 , wherein the conductive layer is selected from the group consisting of a second polysilicon layer, a metal layer, a metal-containing layer, a layer containing one or more conductive materials, and one or more conductive layers.

42. The method of claim 40 , wherein the dielectric layer comprises one or more layers of dielectric material, a third oxide layer, a second nitride layer, or an oxide-nitride-oxide layer.

43. The method of claim 40 , wherein the source and drain select gates and the NAND string form a column of the memory array.

44. The method of claim 40 , wherein forming a first oxide layer on a semiconductor substrate comprises thermally growing an oxide on the semiconductor substrate.

45. The method of claim 40 , wherein forming a second oxide layer on the exposed portion of the substrate comprises thermally growing an oxide on the exposed portion of the substrate.