IP Library Granted Patent US 8,695,212
Granted Patent B2
US 8,695,212 · App. 10/921,225 · Granted Apr 15, 2014

Method for optimizing routing layers and board space requirements for a ball grid array land pattern

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Quick Facts
Patent No.
US 8,695,212
App. No.
10/921,225
Granted
Apr 15, 2014
Kind
B2
Abstract

A method, system, for optimizing routing layers and board space requirements for a ball grid land pattern is described. A number of required pads is determined. A land pattern to yield the required pads is selected. A number of required perimeter routing channels is determined. A size of the land pattern to yield the required perimeter routing channels is optimized. At least one perimeter edge of the land pattern is under populated. In a further aspect, a number of layers is determined when a substrate has multiple layers.

Claims (38)

1. A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising the steps of:

determining a number of required pads;

selecting a land pattern to yield the required pads;

determining a number of required perimeter routing channels; and

optimizing a size of the land pattern to yield the required perimeter routing channels, said optimizing step including under populating at least one perimeter edge of the land pattern on the surface of the printed circuit board to form a first non-fully populated perimeter edge of pads,

wherein the first non-fully populated perimeter edge of pads includes a number of spaces that each represent space for a single pad;

wherein a ratio of pads in the first non-fully populated perimeter edge of pads to the number of spaces is at least two to one (2:1).

2. The method of claim 1 , wherein the first non-fully populated perimeter edge of pads includes a number S of spaces, wherein the number S of spaces is calculated according to

S =INT(( E− 5)/3),

where:

E=a number of pads in the first non-fully populated perimeter edge of pads, if fully populated; and

INT is an INTEGER function, rounded down.

3. The method of claim 1 , wherein said optimizing step comprises:

removing pads from at least one existing fully populated perimeter edge of the land pattern.

4. The method of claim 3 , wherein said removing step includes:

removing a number S of pads, wherein the number S of pads is calculated according to

S =INT(( E− 5)/3),

where:

E=a number of pads in the at least one existing fully populated perimeter edge, when fully populated; and

INT is an INTEGER function, rounded down.

5. The method of claim 3 , wherein a ratio of pads remaining in the at least one fully populated perimeter edge to the number of pads removed from the at least one fully populated perimeter edge is at least two to one (2:1).

6. The method of claim 1 , further comprising:

routing signals, from pads internal to the land pattern, through spaces formed by missing pads in the at least one non-fully populated perimeter edge of pads.

7. The method of claim 6 , wherein said routing step includes:

for each missing pad, routing three signals from pads internal to the land pattern through the space formed by the missing pad in the at least one non-fully populated perimeter edge.

8. The method of claim 1 , wherein said optimizing step comprises:

if the selected land pattern provides excess pads, then removing pads from at least one existing perimeter edge until the required perimeter routing channels are made available; and

if the selected land pattern does not provide excess pads, then adding at least one non-fully populated perimeter edge of pads to the land pattern, wherein the required perimeter routing channels are provided by openings formed by missing pads in the at least one non-fully populated perimeter edge of pads.

9. A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising the steps of:

determining a number of required pads;

selecting a land pattern to yield the required pads;

determining a number of required perimeter routing channels; and

optimizing a size of the land pattern to yield the required perimeter routing channels, said optimizing step including under populating at least one perimeter edge of the land pattern,

wherein a first non-fully populated perimeter edge of pads of the at least one non-fully populated perimeter edge of pads includes a number S of spaces, wherein the number S of spaces is calculated according to

S =INT(( E− 5)/3),

where:

E=a number of pads in the first non-fully populated perimeter edge of pads, if fully populated; and

INT is an INTEGER function, rounded down.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2004
From: SEAMAN, KEVIN L.; WNEK, VERNON M.
To: BROADCOM CORPORATION
Reel/Frame 015443/0081 →