A smart camera system provides focused images to an operator at a host computer by processing digital images at the imaging location prior to sending them to the host computer. The smart camera has a resident digital signal processor for preprocessing digital images prior to transmitting the images to the host. The preprocessing includes image feature extraction and filtering, convolution and deconvolution methods, correction of parallax and perspective image error and image compression. Compression of the digital images in the smart camera at the imaging location permits the transmission of very high resolution color or high resolution grayscale images at real-time frame rates such as 30 frames per second over a high speed serial bus to a host computer or to any other node on the network, including any remote address on the Internet.
1. A camera system comprising:
an image sensor that acquires image data;
a control module that is positioned on or about the image sensor;
an actuator that receives position commands from the control module; and
a host computer, the control module connected to the host computer via a network,
said control module comprising:
a communications unit including:
a component that specifies a unique identification for the communications unit;
a processor;
a non-volatile memory that provides a bootstrap load program of instructions for the processor; and
a volatile program memory that stores a program of instructions for controlling the processor to process the image data, and stores data blocks of desired control state commands and current state control variables for the control module; and
a function unit that drives the actuator, said communications unit electrically coupled to said function unit,
the control module uses the acquire image data and the data blocks to send the position commands to the actuator using the function unit without communicating with the host computer.
2. The camera system according to claim 1 , wherein said communications unit is coupled to said function unit through an error current block having an error current loop input and an error current loop output, said error current block interrupting at least one signal to said actuator from said processor whenever current is interrupted in said error current loop.