Method and system for implementing FI function in KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets
View Patent ↗In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.
1. A method for accelerating cryptography operations, the method comprising:
generating a first signal that controls:
a first stage of substitution in a first substitution circuit and a second substitution circuit; and
a second stage of substitution in a first substitution circuit and a second substitution circuit;
generating a first substituted output from a first portion of an input data by using said first substitution circuit during a first round of said first stage of substitution;
generating a second substituted output from a second portion of said input data by using said second substitution circuit during a second round of said first stage of substitution; and
pipelining transfer of said second portion of said input data for processing with said generated first substituted output from said first substitution circuit during said first round of said first stage of substitution and a third round of said second stage of substitution.
2. The method according to claim 1 , wherein said first signal is a delayed version of a start signal.
3. The method according to claim 1 , wherein said first signal is delayed by one clock cycle from a start signal.
4. The method according to claim 1 , comprising zero-extending said second portion of said input data to said second substitution circuit for said pipelining transfer.
5. The method according to claim 4 , comprising generating a first XORed output by XORing said zero-extended second portion of said input data to said second substitution circuit with said generated first substituted output from said first substitution circuit during said first round of said first stage of substitution.
6. The method according to claim 5 , comprising truncating said first XORed output to generate a first truncated output during a second round of said first stage of substitution.
7. The method according to claim 6 , comprising generating a second XORed output by XORing said first truncated output with said generated second substituted output from said second substitution circuit during said second round of said first stage of substitution.
8. The method according to claim 7 , comprising:
selecting a second subkey; and
XORing said selected second subkey with said second XORed output to generate a third XORed output during said second round of said first stage of substitution.
9. The method according to claim 8 , comprising:
selecting a first subkey; and
XORing said selected first subkey with said first XORed output to generate a fourth XORed output during said second round of said first stage of substitution.
10. The method according to claim 9 , comprising generating a third substituted output from said fourth XORed output by using said first substitution circuit during said third round in said second stage of substitution.
11. The method according to claim 10 , comprising zero-extending said third XORed output for said pipelining transfer during said third round of said second stage of substitution.
12. The method according to claim 11 , comprising generating a fifth XORed output by XORing said zero-extended third XORed output with said generated third substituted output from said first substitution circuit during said third round of said second stage of substitution.
13. The method according to claim 12 , comprising truncating said fifth XORed output to generate a second truncated output during a fourth round of said second stage of substitution.
14. The method according to claim 13 , comprising generating a fourth substituted output from said third XORed output by using said second substitution circuit during said fourth round of said second stage of substitution.
15. The method according to claim 14 , comprising generating a sixth XORed output by XORing said second truncated output with said generated fourth substituted output from said second substitution circuit during said fourth round of said second stage of substitution.
16. The method according to claim 15 , comprising:
selecting a second zero value; and
XORing said selected second zero value with said sixth XORed output to generate a seventh XORed output during said fourth round of said second stage of substitution.
17. The method according to claim 16 , comprising:
selecting a first zero value; and
XORing said selected first zero value with said fifth XORed output to generate an eighth XORed output during said fourth round of said second stage of substitution.
18. The method according to claim 17 , comprising generating an output data by concatenating said seventh XORed output and said eighth XORed output.
19. A system for accelerating cryptography operations, the system comprising:
a first substitution circuit that generates a first substituted output from a first portion of an input data during a first round of a first stage of substitution;
a second substitution circuit that generates a second substituted output from a second portion of said input data during a second round of said first stage of substitution; and
a pipe register that pipeline transfers said second portion of said input data for processing with said generated first substituted output from said first substitution circuit during said first round of said first stage of substitution.
20. The system according to claim 19 , wherein said first substitution circuit generates a third substituted output during a third round of a second stage of substitution.
21. The system according to claim 19 , wherein said second substitution circuit generates a fourth substituted output during a fourth round of a second stage of substitution.
22. The system according to claim 19 , wherein a first multiplexer selects an input to said first substitution circuit for said first stage of substitution and for a second stage of substitution.
23. The system according to claim 19 , wherein a second multiplexer selects an input to said second substitution circuit for said first stage of substitution and a for a second stage of substitution.
24. The system according to claim 19 , wherein a first XOR gate XORs an output of said first substitution circuit with an output of said pipe register.
25. The system according to claim 19 , wherein a second XOR gate XORs an output of a first XOR gate with an output of a third multiplexer.
26. The system according to claim 19 , wherein a third XOR gate XORs an output of said second substitution circuit with an output of a first XOR gate.
27. The system according to claim 19 , wherein a fourth XOR gate XORs an output of a second XOR gate with an output of a fourth multiplexer.
28. The system according to claim 19 , wherein a third multiplexer selects between a first subkey during said first stage of substitution and a first zero value during a second stage of substitution.
29. The system according to claim 19 , wherein a fourth multiplexer selects between a second subkey during said first stage of substitution and a second zero value during a second stage of substitution.
30. A system for accelerating cryptography operations, the system comprising:
one or more circuits comprising a first substitution circuit and a second substitution circuit, said one or more circuits enable generation of a first signal that controls:
a first stage of substitution in said first substitution circuit and said second substitution circuit; and
a second stage of substitution in said first substitution circuit and said second substitution circuit;
said one or more circuits enable generation of a first substituted output from a first portion of an input data by using said first substitution circuit during a first round of said first stage of substitution;
said one or more circuits enable generation of a second substituted output from a second portion of said input data by using said second substitution circuit during a second round of said first stage of substitution; and
said one or more circuits enable pipelining transfer of said second portion of said input data for processing with said generated first substituted output from said first substitution circuit during said first round of said first stage of substitution and a third round of said second stage of substitution.
31. The system according to claim 30 , wherein said one or more circuits enable delaying a start signal to generate said first signal.
32. The system according to claim 30 , wherein said one or more circuits enable delaying a start signal by one clock cycle to generate said first signal.
33. The system according to claim 30 , wherein said one or more circuits enable zero-extending said second portion of said input data to said second substitution circuit for said pipelining transfer.
34. The system according to claim 33 , wherein said one or more circuits enable generation of a first XORed output by XORing said zero-extended second portion of said input data to said second substitution circuit with said generated first substituted output from said first substitution circuit during said first round of said first stage of substitution.
35. The system according to claim 34 , wherein said one or more circuits enable truncation of said first XORed output to generate a first truncated output during a second round of said first stage of substitution.
36. The system according to claim 35 , wherein said one or more circuits enable generation of a second XORed output by XORing said first truncated output with said generated second substituted output from said second substitution circuit during said second round of said first stage of substitution.
37. The system according to claim 36 , wherein said one or more circuits enable selection of a second subkey; and
said one or more circuits enable XORing of said selected second subkey with said second XORed output to generate a third XORed output during said second round of said first stage of substitution.
38. The system according to claim 37 , wherein said one or more circuits enable selection of a first subkey; and
said one or more circuits enable XORing of said selected first subkey with said first XORed output to generate a fourth XORed output during said second round of said first stage of substitution.
39. The system according to claim 38 , wherein said one or more circuits enable generation of a third substituted output from said fourth XORed output by using said first substitution circuit during said third round in said second stage of substitution.
40. The system according to claim 39 , wherein said one or more circuits enable zero-extending of said third XORed output for said pipelining transfer during said third round of said second stage of substitution.
41. The system according to claim 40 , wherein said one or more circuits enable generation of a fifth XORed output by XORing said zero-extended third XORed output with said generated third substituted output from said first substitution circuit during said third round of said second stage of substitution.
42. The system according to claim 41 , wherein said one or more circuits enable truncation of said fifth XORed output to generate a second truncated output during a fourth round of said second stage of substitution.
43. The system according to claim 42 , wherein said one or more circuits enable generation of a fourth substituted output from said third XORed output by using said second substitution circuit during said fourth round of said second stage of substitution.
44. The system according to claim 43 , wherein said one or more circuits enable generation of a sixth XORed output by XORing said second truncated output with said generated fourth substituted output from said second substitution circuit during said fourth round of said second stage of substitution.
45. The system according to claim 44 , wherein said one or more circuits enable selection of a second zero value; and
said one or more circuits enable XORing of said selected second zero value with said sixth XORed output to generate a seventh XORed output during said fourth round of said second stage of substitution.
46. The system according to claim 45 , wherein said one or more circuits enable selection of a first zero value; and
said one or more circuits enable XORing of said selected first zero value with said fifth XORed output to generate an eighth XORed output during said fourth round of said second stage of substitution.
47. The system according to claim 46 , wherein said one or more circuits enable generation of an output data by concatenating said seventh XORed output and said eighth XORed output.