Semiconductor integrated circuit device
View Patent ↗Interconnections are formed over an interlayer insulating film which covers MISFETQ 1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
1. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining active regions and dummy regions not functioning as an element;
element isolation insulating films filled in said trenches;
dummy interconnections formed over said substrate not functioning as an element,
wherein said dummy regions are regularly arranged at a scribing area and at a pad region, respectively,
wherein said dummy interconnections are regularly arranged at said scribing area and at said pad region, respectively.
2. A semiconductor integrated circuit device according to claim 1 , wherein said dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said action region,
wherein said dummy region does not serve as a part of a MISFET.
3. A semiconductor integrated circuit device according to claim 1 , wherein said dummy interconnection is formed by the same level layer as interconnections of a memory device.
4. A semiconductor integrated circuit device according to claim 1 , wherein said dummy interconnection is formed by the same level layer as interconnections functioning as bit lines of a dynamic random access memory.
5. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining an active region and dummy regions not functioning as an element such that an MISFET (Qt) includes a source region and a drain region formed in said active region;
element isolation insulating films filled in said trenches;
an interconnection formed over said substrate and electrically connecting one of said source region and said drain region; and
dummy interconnections formed over said substrate and not functioning as an element,
wherein said dummy interconnections are formed by the same level layer as interconnections,
wherein said dummy regions are regularly arranged at a scribing area and at a pad region, respectively,
wherein said dummy interconnections are regularly arranged at said scribing area and at said pad region, respectively.
6. A semiconductor integrated circuit device according to claim 5 , wherein said MISFET comprises an MISFET of a memory device.
7. A semiconductor integrated circuit device according to claim 5 , wherein said MISFET comprises an MISFET of a memory cell of a dynamic random access memory,
wherein said interconnection is a bit line of said dynamic random access memory.
8. A semiconductor integrated circuit device according to claim 5 , wherein a capacitor element (SN) of said memory cell is formed over said interconnection.
9. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining active regions and dummy regions not functioning as an element;
element isolation insulating films filled in said trenches;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are regularly arranged at a scribing area, respectively.
10. A semiconductor integrated circuit device according to claim 9 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said dummy region does not serve as a part of a MISFET,
wherein said second dummy interconnection is formed by the same level layer as interconnections of a memory device.
11. A semiconductor integrated circuit device according to claim 9 , wherein said dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said second dummy interconnection is formed by the same level layer as interconnections functioning as bit lines of a dynamic random access memory.
12. A semiconductor integrated circuit device according to claim 9 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.
13. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining an active region and dummy regions not functioning as an element such that an MISFET (Qt) includes a source region and a drain region formed in said active region;
element isolation insulating films filled in said trenches;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections;
an interconnection formed over said first interlayer insulating film and electrically connecting one of said source region and said drain region; and
second dummy interconnections formed over said first interlayer insulating film not functioning as an element,
wherein said second dummy interconnections are formed by the same level layer as interconnections,
wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are regularly arranged at a scribing area, respectively.
14. A semiconductor integrated circuit device according to claim 13 , wherein said MISFET comprises an MISFET of a memory device.
15. A semiconductor integrated circuit device according to claim 13 , wherein said MISFET comprises an MISFET of a memory cell of a dynamic random access memory,
wherein said interconnection is a bit line of said dynamic random access memory.
16. A semiconductor integrated circuit device according to claim 13 , wherein a capacitor element (SN) of said memory cell is formed over said interconnection.
17. A semiconductor integrated circuit device according to claim 13 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.
18. A semiconductor integrated circuit device comprising:
a first trench formed in a semiconductor substrate, said first trench surrounding active regions;
a second trench formed in said semiconductor substrate, said second trench surrounding dummy regions not function as an element;
element isolation insulating films filled in said first trench and said second trench;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are regularly arranged at a scribing area, respectively.
19. A semiconductor integrated circuit device according to claim 18 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said dummy region does not serve as a part of a MISFET,
wherein said second dummy interconnection is formed by the same level layer as interconnections of a memory device.
20. A semiconductor integrated circuit device according to claim 18 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said second dummy interconnection is formed by the same level layer as interconnections functioning as bit lines of a dynamic random access memory.
21. A semiconductor integrated circuit device according to claim 18 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.
22. A semiconductor integrated circuit device comprising:
a first trench formed in a semiconductor substrate, said first trench surrounding active regions;
a second trench formed in said semiconductor substrate, said second trench surrounding dummy regions not function as an element;
element isolation insulating films filled in said first trench and said second trench;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections;
an interconnection formed over said first interlayer insulating film and electrically connecting one of said source region and said drain region; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said second dummy interconnections are formed by the same level layer as interconnections,
wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are regularly arranged at a scribing area, respectively.
23. A semiconductor integrated circuit device according to claim 22 , wherein said MISFET comprises an MISFET of a memory device.
24. A semiconductor integrated circuit device according to claim 23 , wherein said MISFET comprises an MISFET of a memory cell of a dynamic random access memory,
wherein said interconnection is a bit line of said dynamic random access memory.
25. A semiconductor integrated circuit device according to claim 23 , wherein a capacitor element (SN) of said memory cell is formed over said interconnection.
26. A semiconductor integrated circuit device according to claim 23 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said dummy interconnections.
27. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining active regions and dummy regions not functioning as an element;
element isolation insulating films filled in said trenches;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are arranged at a scribing area.
28. A semiconductor integrated circuit device according to claim 27 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said dummy region does not serve as a part of a MISFET,
wherein said second dummy interconnection is formed by the same level layer as interconnections of a memory device.
29. A semiconductor integrated circuit device according to claim 27 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said second dummy interconnection is formed by the same level layer as interconnections functioning as bit lines of a dynamic random access memory.
30. A semiconductor integrated circuit device according to claim 27 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.
31. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining an active region and dummy regions not functioning as an element such that an MISFET (Qt) includes a source region and a drain region formed in said active region;
element isolation insulating films filled in said trenches;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections;
an interconnection formed over said first interlayer insulating film and electrically connecting one of said source region and said drain region; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said second dummy interconnections are formed by the same level layer as interconnections,
wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are arranged at a scribing area.
32. A semiconductor integrated circuit device according to claim 31 , wherein said MISFET comprises an MISFET of a memory device.
33. A semiconductor integrated circuit device according to claim 31 , wherein said MISFET comprises an MISFET of a memory cell of a dynamic random access memory,
wherein said interconnection is a bit line of said dynamic random access memory.
34. A semiconductor integrated circuit device according to claim 31 , wherein a capacitor element (SN) of said memory cell is formed over said interconnection.
35. A semiconductor integrated circuit device according to claim 31 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.
36. A semiconductor integrated circuit device comprising:
a first trench formed in a semiconductor substrate, said first trench surrounding active regions;
a second trench formed in said semiconductor substrate, said second trench surrounding dummy regions not function as an element;
element isolation insulating films filled in said first trench and said second trench;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are arranged at a scribing area.
37. A semiconductor integrated circuit device according to claim 36 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said dummy region does not serve as a part of a MISFET,
wherein said second dummy interconnection is formed by the same level layer as interconnections of a memory device.
38. A semiconductor integrated circuit device according to claim 36 , wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said active region serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said active region,
wherein said second dummy interconnection is formed by the same level layer as interconnections functioning as bit lines of a dynamic random access memory.
39. A semiconductor integrated circuit device according to claim 36 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.
40. A semiconductor integrated circuit device comprising:
a first trench formed in a semiconductor substrate, said first trench surrounding active regions;
a second trench formed in said semiconductor substrate, said second trench surrounding dummy regions not function as an element;
element isolation insulating films filled in said first trench and said second trench;
first dummy interconnections formed over said substrate and not functioning as an element;
a first interlayer insulating film formed over said first dummy interconnections;
an interconnection formed over said first interlayer insulating film and electrically connecting one of said source region and said drain region; and
second dummy interconnections formed over said first interlayer insulating film and not functioning as an element,
wherein said second dummy interconnections are formed by the same level layer as interconnections,
wherein said first dummy interconnections are formed by the same level layer as a gate electrode of a MISFET,
wherein said dummy regions, said first dummy interconnections and said second dummy interconnections are arranged at a scribing area.
41. A semiconductor integrated circuit device according to claim 40 , wherein said MISFET comprises an MISFET of a memory device.
42. A semiconductor integrated circuit device according to claim 40 , wherein said MISFET comprises an MISFET of a memory cell of a dynamic random access memory,
wherein said interconnection is a bit line of said dynamic random access memory.
43. A semiconductor integrated circuit device according to claim 40 , wherein a capacitor element (SN) of said memory cell is formed over said interconnection.
44. A semiconductor integrated circuit device according to claim 40 , wherein said first dummy interconnections are formed over said dummy regions,
wherein said second dummy interconnections are formed over said first dummy interconnections.