Resistor ladder interpolation for PGA and DAC
View Patent ↗A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
1. A voltage interpolation circuit comprising:
a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors;
an amplifier;
first and second capacitors connected together at their respective first terminals and to an input of the amplifier;
a first plurality of switches connecting respective taps to a second terminal of the first capacitor; and
a second plurality of switches connecting respective taps to a second terminal of the second capacitor,
wherein an output voltage of the amplifier is interpolated by controlling the first and second pluralities of switches; and
wherein a first switch from the first plurality of switches and a second switch from the second plurality of switches are each connected to a common voltage tap between adjacent resistors in the resistive ladder.
2. The voltage interpolation circuit of claim 1 , wherein the amplifier is a buffer amplifier.
3. A differential voltage interpolation circuit comprising:
a first resistive ladder connected between a positive voltage input and a termination resistor, and having a first plurality of resistors with voltage taps between the resistors;
a first amplifier;
first and second capacitors connected together at their respective first terminals and to an input of the first amplifier;
a first plurality of switches connecting the voltage taps of the first resistive ladder to a second terminal of the first capacitor and a second terminal of the second capacitor,
a second resistive ladder connected between a negative voltage input and the termination resistor, and having a second plurality of resistors with voltage taps between the resistors;
a second amplifier;
third and fourth capacitors connected together at their respective first terminals and to an input of the second amplifier;
a second plurality of switches connecting the voltage taps of the second resistive ladder to a second terminal of the third capacitor and a second terminal of the fourth capacitor,
wherein a differential output voltage of the first and second amplifiers is interpolated by controlling the first and second pluralities of switches; and
wherein a first switch and a second switch from the first plurality of switches are connected to a first common voltage tap between adjacent resistors in the first resistive ladder; and
wherein a third switch and a fourth switch from the second plurality of switches are each connected to a second common voltage tap between adjacent resistors in the second resistive ladder.
4. A voltage interpolation circuit comprising:
a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors;
first and second transistors connected together at their respective sources and to a current source, and having their drains connected to a positive supply;
a first plurality of switches connecting respective taps to a gate of the first transistor; and
a second plurality of switches connecting the respective taps to a gate of the second transistor,
wherein an output voltage at sources of the transistors is interpolated by controlling the first and second pluralities of switches.
5. A voltage interpolation circuit comprising:
a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors;
an amplifier;
a first plurality of switches connecting respective taps to an input of the amplifier; and
a second plurality of switches connecting the respective taps to the fused input of the amplifier,
wherein an output voltage of the amplifier is interpolated by controlling the first and second pluralities of switches; and
wherein a first switch from the first plurality of switches and a second switch from the second plurality of switches are each connected to a common voltage tap between adjacent resistors in the resistive ladder.
6. A voltage interpolation circuit comprising:
a resistive ladder connected between a voltage input and one of a ground terminal and termination resistor and having a plurality of resistors with voltage taps between the resistors;
means for amplification;
a first plurality of switches connecting respective taps to a first terminal of the means for amplification; and
a second plurality of switches connecting the respective taps to a second terminal of the means for amplification,
wherein an output voltage of the means for amplification is interpolated by controlling the first and second pluralities of switches; and
wherein a first switch from the first plurality of switches and a second switch from the second plurality of switches are each connected to a common voltage tap between adjacent resistors in the resistive ladder.
7. The voltage interpolation circuit of claim 1 , wherein a switch from the first plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the second terminal of the first capacitor.
8. The voltage interpolation circuit of claim 1 , wherein a switch from the second plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the second terminal of the second capacitor.
9. The differential voltage interpolation circuit of claim 3 , wherein a first switch from the first plurality of switches allows the positive voltage input to bypass the first resistive ladder and be coupled to the second terminal of the first capacitor and a second switch from the first plurality of switches allows the positive voltage input to bypass the first resistive ladder and be coupled to the second terminal of the second capacitor.
10. The differential voltage interpolation circuit of claim 3 , wherein a first switch from the second plurality of switches allows the negative voltage input to bypass the second resistive ladder and be coupled to the second terminal of the third capacitor and a second switch from the second plurality of switches allows the negative voltage input to bypass the second resistive ladder and be coupled to the second terminal of the second capacitor.
11. The voltage interpolation circuit of claim 4 , wherein a switch from the first plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the gate of the first transistor.
12. The voltage interpolation circuit of claim 4 , wherein a switch from the second plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the gate of the second transistor.
13. The voltage interpolation circuit of claim 5 , wherein a switch from the first plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the single fused input of the amplifier.
14. The voltage interpolation circuit of claim 5 , wherein a switch from the second plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the single fused input of the amplifier.
15. The voltage interpolation circuit of claim 6 , wherein a switch from the first plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the first terminal of the means for amplification.
16. The voltage interpolation circuit of claim 6 , wherein a switch from the second plurality of switches allows the voltage input to bypass the resistive ladder and be coupled to the second terminal of the means for amplification.