Method and apparatus for detecting a packet error in a wireless communications system with minimum overhead using embedded error detection capability of turbo code
View Patent ↗The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability in a turbo code itself to perform error detection following turbo decoding. Specifically, since the two constituent encoders of a turbo encoder that are used to encode a data packet produce two systematic codes that share the same systematic bits one code, one is used to serve as the parity check for the other. The sign of the log likelihood ratio (LLR) of each systematic bit in a block of decoded data calculated at the end of a turbo decoding cycle is compared with the sign of the LLR of each corresponding bit that was calculated at a previous turbo decoding cycle. If the signs of the LLRs for each comparison do not agree, then a packet error is determined to have occurred; otherwise no packet error is detected.
1. A method for detecting an error in a block of decoded bits at a turbo decoder, the method comprising:
comparing, on a bit-by-bit basis, a first set of decoded systematic bit values for a first constituent code with a corresponding second set of decoded systematic bit values for a second constituent code,
each of the first and second sets of decoded systematic bit values being generated during a first iteration of a turbo decoding iteration cycle, and
each decoded systematic bit value in the first and second sets of decoded systematic bit values being represented by a sign of a log likelihood ratio, wherein the comparing step includes,
comparing signs of the log likelihood ratios for corresponding bits of the first and second sets of decoded systematic bit values; and
determining, from the results of the bit-by-bit comparisons of the signs of the log likelihood ratios, whether or not there is an error in the decoded systematic bit values in the block of decoded bits determined at the end of the first turbo decoding cycle.
2. The method of claim 1 , wherein the step of determining determines that there is an error if one or more comparisons of corresponding bit values does not match.
3. The method of claim 1 , wherein the step of determining determines that there is no error if the comparisons of corresponding bit values all match.
4. The method of claim 1 , wherein the first iteration of the turbo decoding iteration cycle includes a first turbo decoding cycle in which a first turbo constituent code is decoded to generate the first set of decoded systematic bit values and a second turbo decoding cycle in which a second turbo constituent code is decoded to generate the second set of decoded systematic bit values.
5. The method of claim 1 , wherein the step of determining determines that there is an error if one or more comparisons of the signs of log likelihood ratios associated with corresponding bits does not match.
6. The method of claim 1 , wherein the step of determining determines that there is no error if the comparisons of log likelihood ratios associated with corresponding bits values all match.
7. An apparatus for detecting an error in a block of bits decoded by a turbo decoder that includes a first constituent turbo decoder and a second constituent turbo decoder, the apparatus comprising:
means for comparing, on a bit-by-bit basis, a first set of decoded systematic bit values for a first constituent code with a corresponding second set of decoded systematic bit values for a second constituent code,
each of the first and second sets of decoded systematic bit values being generated during a first iteration of a turbo decoding iteration cycle, and
each decoded systematic bit value in the first and second sets of decoded systematic bit values being represented by a sign of a log likelihood ratio, wherein
the comparing means compares, signs of the log likelihood ratios for corresponding bits of the first and second sets of decoded systematic bit values; and
means for determining, from the results of the bit-by-bit comparisons of the signs of the log likelihood ratios, whether or not there is an error in the decoded systematic bit values in the block of decoded bits determined at the end of the first turbo decoding cycle.
8. The apparatus of claim 7 , wherein the determining means determines that there is an error if one or more comparisons made by the comparing means of corresponding bit values does not match.
9. The apparatus of claim 7 , wherein the determining means determines that there is no error if the comparisons made by the comparing means of corresponding bit values all match.
10. The apparatus of claim 7 , wherein the determining means determines that there is an error if one or more comparisons made by the comparing means of corresponding bit values does not match.
11. The apparatus of claim 7 , wherein the determining means determines that there is no error if the comparisons made by the comparing means of corresponding bit values all match.
12. The apparatus of claim 7 , wherein the first iteration of the turbo decoding iteration cycle includes a first turbo decoding cycle in which a first turbo constituent code is decoded to generate the first set of decoded systematic bit values and a second turbo decoding cycle in which a second turbo constituent code is decoded to generate the second set of decoded systematic bit values.