Thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
1. A thin film transistor array panel comprising:
a substrate;
a gate line formed on the substrate and including lower and upper films;
a gate insulating layer fanned on the gate line;
a semiconductor layer formed on the gate insulating layer;
source and drain electrodes formed on the semiconductor layer, disposed opposite each other with respect to a first portion of the semiconductor layer, and including lower and upper films having edges that are disposed adjacent to the first portion of the semiconductor layer and do not coincide with each other;
a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing the first portion of the semiconductor layer; and
a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.
2. The thin film transistor array panel of claim 1 , further comprising first and second redundant electrodes disposed on the source and the drain electrodes, respectively, and comprising the same layer as the pixel electrode.
3. The thin film transistor array panel of claim 2 , wherein the opening further exposes portions of the lower films of the source and the drain electrodes.
4. The thin film transistor array panel of claim 3 , wherein the first and the second redundant electrodes contact the exposed portions of the lower films of the source and the drain electrodes, respectively.
5. The thin film transistor array panel of claim 4 , wherein the first and the second redundant electrodes have at least an edge that coincides with an edge of the exposed portions of the lower films of the source and the drain electrodes, respectively.
6. The thin film transistor array panel of claim 5 , wherein the opening has at least an edge covered by the first or the second redundant electrodes.
7. The thin film transistor array panel of claim 1 , wherein the first contact hole exposes a portion of the lower film of the drain electrode and a portion of the gate insulating layer adjacent thereto.
8. The thin film transistor array panel of claim 1 , wherein the upper film of the drain electrode has at least an edge that coincides with an edge of the first contact hole.
9. The thin film transistor array panel of claim 1 , further comprising an insulator disposed on the exposed first portion of the semiconductor layer.
10. The thin film transistor array panel of claim 9 , wherein the insulator comprises a columnar spacer.
11. The thin film transistor array panel of claim 1 , wherein the lower films of the source and the drain electrodes comprise Cr and the upper films of source and the drain electrodes comprise Al.
12. The thin film transistor array panel of claim 1 , wherein the pixel electrode comprises IZO.