Integrated circuit package having inductance loop formed from a bridge interconnect
An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.
1. An oscillator circuit, comprising:
an active oscillator having two output nodes;
an inductor loop coupled to the output nodes; and
at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including:
(a) a first conductor connecting a first bonding pad on the chip to a first input/output pin of the package;
(b) a second conductor connecting a second bonding pad on the chip to a second input/output pin of the package; and
(c) a third conductor which includes a metallization layer connecting the first input/output pin to the second input/output pin.
2. The oscillator circuit of claim 1 , wherein the first conductor and the second conductor are bonding wires.
3. The oscillator circuit of claim 1 , wherein the metallization layer is on a surface of the substrate.
4. The oscillator circuit of claim 1 , wherein the metallization layer is included in a sub-surface layer of the substrate.
5. The oscillator circuit of claim 1 , wherein the first input/output pin and the second input/output pin are adjacent pins.
6. The oscillator circuit of claim 1 , wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.
7. An oscillator circuit, comprising:
an active oscillator having two output nodes;
an inductor loop coupled to the output nodes; and
at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including:
(a) a first conductor connecting a first bonding pad on the chip to a first input/output pin of the package; and
(b) a second conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and contact one another.
8. The oscillator circuit of claim 7 , wherein the first conductor and the second conductor are bonding wires.