Power module flip chip package
View Patent ↗A power module flip chip package is provided. The power module flip chip package includes a package carrier having a front surface and a back surface facing the front surface, and a power semiconductor device electrically connected to the front surface of the package carrier via conductive bumps. The conductive bumps are electrically connected to a gate terminal, a source terminal, and a drain terminal of the power semiconductor device. The power module flip chip package has reduced resistance and inductance and improved reliability.
1. A power module flip chip package comprising:
a package carrier having a front surface on one side and a back surface on an opposite side;
one or more power vertical metal oxide semiconductor field effect transistors electrically connected to the front surface of the package via a first set of conductive bumps located between the power semiconductor and the front surface of the package carrier, wherein the conductive bumps are electrically connected to a gate terminal, a source terminal, and a drain terminal of the power vertical metal oxide semiconductor field effect transistors;
a second set of conductive bumps located on the back side of the carrier and connected to the first set of conductive bumps;
a protective material covering the power vertical metal oxide semiconductor field effect transistor(s) and enclosing the power vertical metal oxide semiconductor transistor(s) and the first set of conductive bumps;
wherein the power vertical metal oxide semiconductor field effect transistor(s) comprises a conductive housing in electrical contact with the drain and having portions extending away from the drain and terminating in one or more conductive bumps in substantially the same plane as the first set of conductive bumps.
2. The power module flip chip package of claim 1 wherein the second set of conductive bumps is not covered by said protective material.
3. The power module flip chip package of claim 1 wherein the protective material is a plastic encapsulant.
4. The power module flip chip package of claim 1 further comprising an auxiliary device die disposed on the front side of the carrier and having a third set of conductive bumps for connecting the auxiliary device to the power vertical metal oxide semiconductor field effect transistor and to the second set of conductive bumps.
5. The power module flip chip package of claim 1 wherein the drain of the power vertical metal oxide semiconductor field effect transistor(s) is or are electrically connected to the conductive housing via a conductive solder.
6. The power module flip chip package of claim 1 further comprising a heat sink.
7. The power module flip chip package of claim 6 wherein the heat sink is coupled to the back surface of the package carrier.
8. The power module flip chip package of claim 6 wherein the heat sink is coupled to the package carrier and over the protective material.
9. The power module flip chip package of claim 8 wherein the heat sink is on the protective material that covers the power vertical metal oxide semiconductor field effect transistor(s)
10. The power module flip chip package of claim 8 wherein the heat sink is spaced from the protective material that covers the power vertical metal oxide semiconductor field effect transistor(s).