Method and system for programming a plurality of different memory devices during development and production with a single controllable interface tool
Methods and systems for programming a plurality of memory devices during development and production are provided. Aspects of the method may include receiving configuration information from the plurality of memory devices, which are coupled to a single programming host. At least one configuration instruction may be generated by the single programming host based on the received configuration information. The plurality of memory devices may be simultaneously configured via the generated at least one configuration instruction. The configuration information may be received via a communication interface, which couples the single programming host to the plurality of memory devices. The communication interface may comprise a serial or parallel interface. The communication interface may also comprise a wired or wireless interface. The method may further include determining whether each of the plurality of memory devices is a hardware and/or a software controllable device.
1 . A method for programming a plurality of memory devices during development and production, the method comprising:
receiving configuration information from the plurality of memory devices, which are coupled to a single programming host;
generating at least one configuration instruction by said single programming host based on said received configuration information; and
simultaneously configuring the plurality of memory devices via said generated at least one configuration instruction.
2 . The method of claim 1 , wherein said configuration information is received via a communication interface, which couples said single programming host to the plurality of memory devices.
3 . The method of claim 2 , wherein said communication interface comprises a serial or parallel interface.
4 . The method of claim 2 , wherein said communication interface comprises a wireless or wired interface.
5 . The method of claim 1 , further comprising determining whether each of the plurality of memory devices is a hardware controllable device.
6 . The method of claim 1 , further comprising determining whether each of the plurality of memory devices is a software controllable device.
7 . The method of claim 6 , further comprising, if said each of the plurality of memory devices is not a software controllable device, initializing said each of the plurality of memory devices with configuration software.
8 . The method of claim 1 , further comprising verifying integrity of each of the plurality of memory devices after said simultaneous configuring of the plurality of memory devices.
9 . The method of claim 8 , wherein said verification of integrity utilizes at least one of a cyclic redundancy check (CRC) and a checksum.
10 . The method of claim 1 , further comprising acquiring an identity of each of the plurality of memory devices prior to said simultaneous configuring.
11 . The method of claim 10 , further comprising validating said acquired identity utilizing on-chip vendor identification (ID) information.
12 . A machine-readable storage having stored thereon, a computer program having at least one code section for programming a plurality of memory devices during development and production, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
receiving configuration information from the plurality of memory devices, which are coupled to a single programming host;
generating at least one configuration instruction by said single programming host based on said received configuration information; and
simultaneously configuring the plurality of memory devices via said generated at least one configuration instruction.
13 . The machine-readable storage of claim 12 , wherein said configuration information is received via a communication interface, which couples said single programming host to the plurality of memory devices.
14 . The machine-readable storage of claim 13 , wherein said communication interface comprises a serial or parallel interface.
15 . The machine-readable storage of claim 13 , wherein said communication interface comprises a wired or wireless interface.
16 . The machine-readable storage of claim 12 , further comprising code for determining whether each of the plurality of memory devices is a hardware controllable device.
17 . The machine-readable storage of claim 12 , further comprising code for determining whether each of the plurality of memory devices is a software controllable device.
18 . The machine-readable storage of claim 17 , further comprising, if said each of the plurality of memory devices is not a software controllable device, code for initializing said each of the plurality of memory devices with configuration software.
19 . The machine-readable storage of claim 12 , further comprising code for verifying integrity of each of the plurality of memory devices after said simultaneous configuring of the plurality of memory devices.
20 . The machine-readable storage of claim 19 , wherein said verification of integrity utilizes at least one of a cyclic redundancy check (CRC) and a checksum.
21 . The machine-readable storage of claim 12 , further comprising code for acquiring an identity of each of the plurality of memory devices prior to said simultaneous configuring.
22 . The machine-readable storage of claim 21 , further comprising code for validating said acquired identity utilizing on-chip vendor ID information.
23 . A system for programming a plurality of memory devices during development and production, the system comprising:
at least one processor that receives configuration information from the plurality of memory devices, which are coupled to a single programming host;
the at least one processor generates at least one configuration instruction based on said received configuration information; and
the at least one processor simultaneously configures the plurality of memory devices via said generated at least one configuration instruction.
24 . The system of claim 23 , wherein said configuration information is received via a communication interface, which couples said at least one processor to the plurality of memory devices.
25 . The system of claim 24 , wherein said communication interface comprises a serial or parallel interface.
26 . The system of claim 24 , wherein said communication interface comprises a wired or wireless interface.
27 . The system of claim 23 , wherein the at least one processor determines whether each of the plurality of memory devices is a hardware controllable device.
28 . The system of claim 23 , wherein the at least one processor determines whether each of the plurality of memory devices is a software controllable device.
29 . The system of claim 28 , wherein, if said each of the plurality of memory devices is not a software controllable device, the at least one processor initializes said each of the plurality of memory devices with configuration software.
30 . The system of claim 23 , wherein the at least one processor verifies integrity of each of the plurality of memory devices after said simultaneous configuring of the plurality of memory devices.
31 . The system of claim 30 , wherein said verification of integrity utilizes at least one of a cyclic redundancy check (CRC) and a checksum.
32 . The system of claim 23 , wherein the at least one processor acquires an identity of each of the plurality of memory devices prior to said simultaneous configuring.
33 . The system of claim 32 , wherein the at least one processor validates said acquired identity utilizing on-chip vendor ID information.