Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
View Patent ↗A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (S in (delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.
1. A differential amplifier comprising:
(a) first and second transistors having respective first and second drains through which respective first and second drain currents flow, the sum of the first and second drain currents defining a relative constant;
(b) first and second variable drain impedances respectively coupled to the first and second drains, each of the variable drain impedances having an inductance (L), a capacitance (C) and a resistance (R), wherein at least two of said R, L and C are adjustable so that a first output voltage versus input voltage transfer function of the differential amplifier can be tuned at least at 0 Hz (base frequency) and at a higher frequency; and
(c) at least first and second different output tapping terminals provided in each of the first and second variable drain impedances so as to respectively output from each of the first and second variable drain impedances, corresponding first and second output signals having respectively different magnitudes.
2. The differential amplifier of claim 1 wherein:
one of the first and second output signals has its magnitude adjusted so to define an essentially unity base gain at its corresponding output tapping terminal.
3. The differential amplifier of claim 1 wherein:
at least said resistance (R) of each of the first and second variable drain impedances is programmably adjustable.
4. The differential amplifier of claim 1 wherein:
each drain impedance includes at least first and second inductors each respectively connecting to a respective one but not the other of the first and second output tapping terminals of that drain impedance.
5. The differential amplifier of claim 4 wherein:
each drain impedance includes a variable capacitor coupled between the first and second inductors.
6. The differential amplifier of claim 4 wherein:
each drain impedance further includes a third inductor interposed between a power rail and said first and second inductors.
7. The differential amplifier of claim 4 wherein:
said first and second inductors of each drain impedance define a mutually coupled inductive system.
8. The differential amplifier of claim 7 wherein:
said mutually coupled inductive system has a mutual coupling factor of about one.
9. The differential amplifier of claim 7 wherein:
the first and second inductors of each of the drain impedances are defined by spiral coils disposed respectively and overlappingly in first and second conductive layers of a monolithic integrated circuit.
10. The differential amplifier of claim 6 and further comprising:
a variable resistance coupled to both drain impedances.
11. The differential amplifier of claim 1 and further comprising:
a variable resistance coupled to both drain impedances.
12. The differential amplifier of claim 1 and further comprising:
variable transconductance means having a transconductance factor that is adjustable independently of the adjustable ones of said at least two adjustable ones of L, R and C for thereby providing the differential amplifier with a variable transconductance factor (g m(var) ).
13. The differential amplifier of claim 1 wherein:
at least two of said R, L and C are programmably and independently adjustable.
14. A plurality of DC series-connected differential amplifiers where each of two or more of said amplifiers has at least:
first and second different output tapping terminals in each of complementary current legs of the given differential amplifier, where the first and second output tapping terminals respectively output corresponding first and second output signals having respectively different magnitudes but the same polarity.
15. The plurality of DC series-connected differential amplifiers of claim 14 wherein:
a base gain of the first output tapping terminal of each of the two or more amplifiers is adjustable to achieve unity base gain at said first output tapping terminal.
16. The plurality of DC series-connected differential amplifiers of claim 15 wherein:
a primary delay provided by the first output tapping terminal of each of the two or more amplifiers is adjustable to achieve a predefined amount of signal delay at said first output tapping terminal.
17. A multi-tapped amplifier comprising:
(a) a first input terminal for receiving a corresponding first input signal having DC and AC components;
(b) a first output tap for outputting a corresponding first output signal that constitutes a first amplification of the first input signal in accordance with a first frequency response characteristic, the first output tap having a first capacitance loading the first output tap;
(c) a second output tap for outputting a corresponding second output signal that constitutes a second amplification of the first input signal in accordance with a second frequency response characteristic, the second output tap having a second capacitance loading the second output tap,
wherein the first and second output signals have the same polarity but the second amplification is different than the first amplification, and
wherein the first and second capacitances respectively define frequency response characteristics of the first and second output taps; and
(d) a common amplification adjuster for commonly adjusting the first and second amplifications.
18. The multi-tapped amplifier of claim 17 wherein:
the amplifier has plural current carrying legs; and
said first and second output taps are disposed along the same current carrying leg of the amplifier.
19. The multi-tapped amplifier of claim 17 wherein:
said common amplification adjuster can adjust the first amplification to a value substantially equal to unity and simultaneously adjust the second amplification to a value greater than unity.
20. The multi-tapped amplifier of claim 17 wherein:
the amplifier has plural impedances for loading respective ones of plural active devices; and
said first and second output taps are disposed in a same one of said plural impedances.
21. The multi-tapped amplifier of claim 20 wherein:
each of said impedances includes first and second inductors coupled in a series circuit and the first output tap couples to the series circuit between the first and second inductors.
22. The multi-tapped amplifier of claim 21 wherein:
each of said impedances includes a variable capacitor coupled to said series circuit.
23. The multi-tapped amplifier of claim 22 wherein:
each of said impedances includes a variable resistance means coupled in series with said series circuit.
24. The multi-tapped amplifier of claim 21 wherein:
each of said impedances includes a variable resistance means coupled in series with said series circuit.
25. The multi-tapped amplifier of claim 24 wherein:
each of said impedances includes a third inductor coupled in series with said series circuit.
26. The multi-tapped amplifier of claim 25 wherein:
said variable resistance means is disposed between a power rail of the amplifier and the inductors in said series circuit.
27. The multi-tapped amplifier of claim 17 wherein:
wherein the first and second output signals are differently delayed and differently amplified versions of the first input signal.
28. The multi-tapped amplifier of claim 27 comprising:
a common delay adjuster for commonly adjusting the delays of the first and second output signals.
29. The multi-tapped amplifier of claim 28 wherein:
said common delay adjuster includes a variable capacitance that is inductively de-lumped from said first and second capacitances of the first and second output taps.