Method and system for digital baseband receiver with digital RF/IF/VLIF support in GSM/GPRS/EDGE compliant handsets
View Patent ↗A method and system for digital baseband receiver with digital RF/IF/VLIF support in GSM/GPRS/EDGE compliant handsets. The method may comprise receiving an input signal which may be a digital RF signal, IF or VLIF signals, and the input signal may comprise of I and Q components. The serial digital RF signal may be converted to a parallel digital formatted signal, the latter of which may be transferred to an input of a multiplexer. The received IF signal or VLIF signal may be filtered and transferred to the input of the DU which may convert the VLIF signal to a baseband signal by processing the VLIF signal with a CORDIC algorithm. The DU may bypass processing the IF signal. The output of the DU may be transferred to the input of the multiplexer, such that the multiplexer may select the parallel digital formatted signal or the output of the DU.
1. A method for processing a plurality of signals, comprising:
receiving an input signal;
if said received input signal is a digital RF signal, converting said digital RF signal to a parallel digital formatted signal;
if said received input signal is a VLIF signal, generating a baseband signal by processing said VLIF signal;
if said received input signal is an IF signal, bypassing said processing of said IF signal;
generating a digital output based on one of said parallel digital formatted signal, said generated baseband signal and said bypassed IF signal; and
generating at least one control signal that controls said converting, said bypassing, said generating of said baseband signal and said generating of said digital output.
2. The method according to claim 1 , wherein said received input signal comprises an I component and a Q component.
3. The method according to claim 1 , comprising filtering said VLIF signal.
4. The method according to claim 1 , comprising filtering said IF signal.
5. The method according to claim 1 , wherein said generated digital output comprises an I component and a Q component.
6. The method according to claim 1 , comprising filtering said generated digital output.
7. The method according to claim 1 , wherein said generated digital output is selected from at least a portion of said parallel digital formatted signal and at least a portion of said generated baseband signal.
8. The method according to claim 1 , wherein said generated digital output is selected from at least a portion of said parallel digital formatted signal and at least a portion of said bypassed IF signal.
9. The method according to claim 1 , comprising filtering one or both of: said generated baseband signal and said bypassed IF signal.
10. The method according to claim 1 , comprising receiving at least one control signal that controls said converting, said bypassing, said generating of said baseband signal and said generating of said digital output.
11. A system for processing a plurality of signals, comprising:
one or more circuits that enable reception of an input signal;
said one or more circuits enable conversion of said received input signal to a parallel digital formatted signal if said received input signal is a digital RF signal;
said one or more circuits enable generation of a baseband signal by processing said received input signal if said received input signal is a VLIF signal;
said one or more circuits enable bypassing processing of said received input signal if said received input signal is an IF signal;
said one or more circuits enable generation of a digital output based on one of said parallel digital formatted signal, said generated baseband signal and said bypassed IF signal, and
wherein said one or more circuits enable use of at least one control signal that controls said converting, said bypassing, said generating of said baseband signal and said generating of said digital output.
12. The system according to claim 11 , wherein said received input signal comprises an I component and a Q component.
13. The system according to claim 11 , wherein said one or more circuits enable filtering of said VLIF signal.
14. The system according to claim 11 , wherein said one or more circuits enable filtering of said IF signal.
15. The system according to claim 11 , wherein said generated digital output comprises an I component and a Q component.
16. The system according to claim 11 , wherein said one or more circuits enable filtering of said generated digital output.
17. The system according to claim 11 , wherein said one or more circuits enable selection of at least a portion of said parallel digital formatted signal and at least a portion of said generated baseband signal in generating said generated digital output.
18. The system according to claim 11 , wherein said one or more circuits enable selection of at least a portion of said parallel digital formatted signal and at least a portion of said bypassed IF signal in generating said generated digital output.
19. The system according to claim 11 , wherein said one or more circuits enable filtering of one or both of: said generated baseband signal and said bypassed IF signal.
20. The system according to claim 11 , wherein said one or more circuits enable generation of at least one control signal that controls said converting, said bypassing, said generating of said baseband signal and said generating of said digital output.